Figure 6.14-16 Two-Bit Transfer Mode System Architecture; Figure 6.14-17 Two-Bit Transfer Mode Timing (Master Mode) - Nuvoton ISD94124BYI Technical Reference Manual

SPI0_MISO[1:0]
SPI0_MOSI[1:0]
SPI0 Controller
Master

Figure 6.14-16 Two-Bit Transfer Mode System Architecture

SPI0_SS0/1 pin
SPI0_CLK pin
SPI0_MOSI0 pin
SPI0_MISO0 pin
SPI0_MOSI1 pin
SPI0_MISO1 pin

Figure 6.14-17 Two-Bit Transfer Mode Timing (Master Mode)

6.14.5.9 Dual I/O Mode
The SPI0 controller also supports Dual I/O transfer when setting the DUALIOEN (SPI0_CTL[21]) to
1. Many general SPI flashes support Dual I/O transfer. The DATDIR (SPI0_CTL[20]) is used to
define the direction of the transfer data. When the DATDIR bit is set to 1, the controller will send
the data to external device. When the DATDIR bit is set to 0, the controller will read the data from
the external device. This function supports 8, 16, 24, and 32 bits of length.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
SPI0_CLK
SPI0_SS0/1
TX Data (n)
RX Data (n)
TX Data (n+1)
RX Data (n+1)
Page 689 of 928
SPI_CLK
SPI0_MISO0
SPI_DO
SPI0_MOSI0
SPI_DI
SPI_SS
Slave 0
SPI_CLK
SPI0_MISO1
SPI_DO
SPI0_MOSI1
SPI_DI
SPI_SS
Slave 1
TX Data (n+2)
RX Data (n+2)
TX Data (n+3)
RX Data (n+3)
Rev1.09