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6.15.7 Register Description
CRC Control Register
(CRC_CTL)
Offset
Register
CRC_CTL
CRC_BA+0x00
30
31
CRCMODE
23
22
15
14
7
6
Description
Bits
[31:30]
CRCMODE
[29:28]
DATLEN
[27]
CHKSFMT
[26]
DATFMT
Sep 9, 2019
ISD94100 Series Technical Reference Manual
R/W Description
R/W CRC Control Register
29
28
DATLEN
CHKSFMT
21
20
Reserved
13
12
Reserved
5
4
Reserved
CRC Polynomial Mode
This field indicates the CRC operation polynomial mode.
00 = CRC-CCITT Polynomial mode.
01 = CRC-8 Polynomial mode.
10 = CRC-16 Polynomial mode.
11 = CRC-32 Polynomial mode.
CPU Write Data Length
This field indicates the write data length.
00 = Data length is 8-bit mode.
01 = Data length is 16-bit mode.
1x = Data length is 32-bit mode.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only
DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register
is only DATA[15:0].
Checksum 1's Complement
This bit is used to enable the 1's complement function for checksum result in
CRC_CHECKSUM register.
0 = 1's complement for CRC checksum Disabled.
1 = 1's complement for CRC checksum Enabled.
Write Data 1's Complement
This bit is used to enable the 1's complement function for write data value in CRC_DAT
register.
0 = 1's complement for CRC writes data in Disabled.
1 = 1's complement for CRC writes data in Enabled.
Page 750 of 928
27
26
25
DATFMT
CHKSREV
19
18
17
11
10
9
3
2
1
CHKSINIT
Reset Value
0x2000_0000
24
DATREV
16
8
0
CRCEN
Rev1.09
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