Figure 6.16-10 Conversion Start Delay Timing Diagram - Nuvoton ISD94124BYI Technical Reference Manual

PCLK
PWRITE
SWTRGn
(EADC_SWTRG[n],
n=0~12)
ADC start
ADC Status
ADIFn
(EADC_STATUS2[n],
n=0~3)

Figure 6.16-10 Conversion Start Delay Timing Diagram

ADC conversion can be triggered by external pin EADC0_ST request. Setting the TRGSEL
(EADC_SCTLn[20:16], n=0~12) to 0x01 is to select external trigger input from the EADC0_ST pin.
User can set EXTFEN (EADC_SCTLn[5], n=0~12) and EXTREN (EADC_SCTLn[4], n=0~12) to
enable pin EADC0_ST trigger condition is falling or rising edge. There is a de-bounce circuit to
detect falling or rising edge. If rising edge trigger condition is selected, the low state must be kept
at least 2 PCLK cycles and the following high state must be kept at least 3 PCLK cycles. If falling
edge trigger condition is selected, the high state must be kept at least 2 PCLK cycles and the
following low state must be kept at least 3 PCLK cycles. Pulse that is shorter than this specification
will be ignored. The external trigger timing is shown in Figure 6.16-11
Sep 9, 2019
ISD94100 Series Technical Reference Manual
A/D conversion start
delay time (Td)
Synchronous to
ADC clock delay
1 ADC clock
up to 1 ADC clock
First ADC clock
Idle state
Page 765 of 928
A/D conversion time
Sampling
Hold
End of conversion
Rev1.09