Table 6.13.5-1 Reserved Smbus Address - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc

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Bus Management (SMBus/PMBus Compatible)

This section is relevant only when Bus Management feature is supported.

Introduction

The Bus Management is an I

each other and with the rest of the system. It is based on I

Management provides a control bus for system and power management related tasks.

This peripheral is compatible with the SMBUS specification rev 2.0 (http://smbus.org/specs/) and

PMBUS specification rev 1.2 (http://pmbus.org/).

The System Management Bus Specification refers to three types of devices.

● A slave is a device that receives or responds to a command.

● A master is a device that issues commands, generates the clocks and terminates the transfer.

● A host is a specialized master that provides the main interface to the system's CPU. A host must

be a master-slave and must support the SMBus host notify protocol. Only one host is allowed in a

This Bus Management peripheral is based on I

Device Identification – slave address

Any device that exists on the Bus Management as a slave has a unique address called the Slave

Address. For reference, the following addresses are reserved and must not be used by or assign

to any Bus Management device. (Refer to SMBus specification for detail information)

Slave Address

ISD94100 Series Technical Reference Manual

C interface through which various devices can communicate with

C specification rev 2.1.

General Call Address

CBUS address

Address reserved for different bus format

Reserved for future use

Reserved for ACCESS.bus host

Reserved for ACCESS.bus default address

10-bit slave addressing

Reserved for future use

SMBus Alert Response Address

SMBus Device Default Address

Table 6.13.5-1 Reserved SMBus Address

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C principles of operation. The Bus

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