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Nuvoton ISD61S00 ChipCorder Chip Manuals
Manuals and User Guides for Nuvoton ISD61S00 ChipCorder Chip. We have
1
Nuvoton ISD61S00 ChipCorder Chip manual available for free PDF download: Design Manual
Nuvoton ISD61S00 ChipCorder Design Manual (214 pages)
Telephony Feature Chip
Brand:
Nuvoton
| Category:
Microcontrollers
| Size: 2 MB
Table of Contents
Table of Contents
2
1 General Description
10
2 Features
10
3 Pin Configuration
12
4 Pin Description
13
5 Block Diagram
16
6 Configuration Register Map
17
Configuration Register Groups
17
Register Map
17
7 Device Status
32
Device Status Register
32
8 Functional Description
34
SPI Interface
34
Record and Playback Control
36
COMP_CFG - Compression Configuration
36
COMP_CTRL - Compression Control
38
COMP_SRC - Compression Source
39
CLK_CTRL - Clock Control
39
CFG17 - Update Mode
40
Clock Generation and PLL
40
Phase Locked Loop (PLL) Design Example
41
Pll_Clk
42
Pll_Frac
43
Pll_Ctrl
43
Digital Audio Interface Control
43
Pcm_Cfg
44
Pcm_Tslotl
45
Pcm_Tslotr
45
Pcm_Comp0
45
Pcm_Tslotl1
45
Pcm_Tslotr1
46
Pcm_Comp1
46
Pcm_Tx_Sel
47
Pcm_Rx_Sel
48
GPIO and Interrupt Configuration
48
Port_Cfg
48
Portx_Ie
49
Ie0
49
Ie1
50
Porta_Do
50
Porta_Oe
50
Porta_Pe
50
Porta_Di
51
Porta_Ps
51
Porta_Ds
51
Porta_Af
51
Bit Indirect Index Register R0-R7
53
Microphone Interface and Auxiliary Interface
54
Mic_Ctrl
54
Mic_Bias
55
PSTN Analog Input
60
Ti_Gain
61
Ti_Ctrl
61
Analog Outputs
63
Ana_Out
64
Ana_Ctrl
64
Dtmf_Ctrl
67
Dtmf_Fifo_Ctrl
67
Dtmf_Fifo
68
Dtmf_Fifo_Status
68
Dtmf_Thres
68
Dtmf_Pdt
69
Dtmf_Adt
70
Dtmf_Acct
70
Dtmf_Rx_Data
70
Dtmf_Row_Freq
71
Dtmf_Col_Freq
71
Tip & Tricks
71
DTMF and Arbitrary Tone Generation
72
Tone_Ctrl
73
Tone_Freq_A
73
Tone_Freq_B
74
Tone_Level_A
74
Tone_Level_B
74
Tone_On_Time
74
Tone_Off_Time
75
Tone_Length
75
Tone_Index_0 ~ Tone_Index_A
76
FSK Generation
76
Fske_Ctrl1
78
Fske_Ctrl2
78
Fske_Tx_Data
79
Fske_Status
79
Fske_Gain
79
Fske_Prog
79
Fske_Baud (Sw_Mode = 1)
80
Fske_Mark_Freq (Sw_Mode = 1)
80
Fske_Space_Freq (Sw_Mode = 1)
81
Fske_Test
81
Example FSK Generator Usage
81
FSK Detection
85
Fskd_Ctrl
86
Fskd_Mode
88
Fskd_Adjust
88
Fskd_Status
89
Fskd_Thres
89
Fskd_Judge
90
Fskd_Sync
90
Fskd_Cdet
90
Fskd_Fifo_Ctrl
91
Fskd_Fifo_Dout
92
Fskd_Fifo_Status
92
Fskd_Energy_High_Th
92
Fskd_Energy_Low_Th
93
Fskd_Energy_Tc
93
Fskd_Cdb_Freq_Low_Cnt
93
Fskd_Cdb_Freq_High_Cnt
94
Fskd_Limit_Th
94
Example FSK Detector Usage
95
CAS and Arbitrary Tone (ATD) Detector
99
Cas_Ctrl
101
CAS_THRES_LOW - CAS Detector Low Threshold
102
Cas_Mult
102
Cas_Present
103
Cas_Absent
104
Cas_Status
104
CAS_MODE - Arbitrary Tone Detection Mode
104
Atd_Max_Hfc (Atd_Mode = 1)
105
Atd_Min_Hfc (Atd_Mode = 1)
105
Atd_Max_Lfc (Atd_Mode = 1)
106
Atd_Min_Lfc (Atd_Mode = 1)
106
External Dual-IIR Coefficient (ATD_MODE= 1)
106
FSK_COEFF - FSK Encoder Coefficient RAM Data
107
FSK_COEFF_ADDR - FSK Encoder Coefficient RAM Address
108
Cas_Max_Hfc (Fine_Tune = 1)
108
Cas_Min_Hfc (Fine_Tune = 1)
109
Cas_Max_Lfc (Fine_Tune = 1)
109
Cas_Min_Lfc (Fine_Tune = 1)
109
Arbitrary Tone Detector Example
110
Voice Energy Detection (Speech Energy Detection)
115
Vd_Ctrl
116
Vd_Status
116
Vd_Thres
116
Vd_Energy
116
Call Progress Tone Detector
117
Cpt_Ctrl
117
Cpt_Status
118
Cpt_Thres_H
118
Cpt_Thres_L
118
Cpt_Energy
119
Ring Detection and Pulse / Period Width Measurement
119
Rng_Ctrl
120
Rng_State
122
Rng_Cntr
122
Rng_Latch
123
Timer
123
Time_Targ
124
Time_Cnt
124
Gain Stage and Mixer
124
Gs_Ctrl
128
CODEC EC Gain Stages
129
Aecin Path Mixing Gain Control
130
Lecin Path Mixing Gain Control
130
REC Path Mixing Gain Control Registers
131
I2Slin Path Mixing Gain Control Registers
132
I2Srin Path Mixing Gain Control Registers
132
Mixer Source Enable Registers
133
Air and Line CODEC
133
AC_EN, LC_EN - Air /Line CODEC Enable Register
134
AC_CTRL, LC_CTRL - Air /Line CODEC Dither Control
135
AC_ADCG, LC_ADCG - Air/Line CODEC ADC Gain
135
AC_DACG, LC_DACG - Air/Line CODEC DAC Gain
135
Ringer Tone Generator
136
PWM Clock
137
PWM Tone1 Control
137
PWM Tone1 Frequency
138
PWM Tone2 Control
138
PWM Tone2 Frequency
139
9 Acoustic Processing Block
139
Full/Half AEC Block Diagram
139
Control Register Memory Map
141
Threshold and Power Calculation
145
Control Registers
145
Config
146
Reset
146
Ec_Belta
147
As_Coeff
148
Double Talk Detector Control Registers
148
Function
149
Dt_Long_Tc
149
Dt_Short_Tc
149
Double Talk Detector Parameters
150
Divergence
150
Voice Detector Control Registers
151
Function
151
Vd_Long_Tc
151
Vd_Short_Tc
151
Voice Detector Parameters
151
Vd_Ave_Thresh
153
AS1 & AS2 Control Registers
153
Function
153
As1_Build_Up_Time
153
As1_Max_Atten
153
As2_Build_Up_Time
154
As2_Max_Atten
154
Noise Suppressor Registers
154
Function
154
Ns_Power_Attack_Tc
155
Ns_Atten
155
Ns_Active_Threshold
155
Soft Clip (SC) Control Registers
156
Functional Description
156
Sc_Ctrl
156
Sc_Normal_Index
157
Sc_Low_Index
158
Sc_Thresh
158
Sc_Power_Attack_Tc
158
Sc_Gain_Tc
159
State Read Back Registers
159
Functional Description
159
Power Monitor
159
Signal Monitor
160
Automatic Gain Control
161
Agc_Ctrl
162
Agc_Init_Gain
163
Agc_Gain_Hold
163
Agc_Inc_Dec
163
Agc_Atk_Dcy
163
Agc_Gain_Read
164
Agc_State
164
Agc_Pwr_Tc
164
Agc_Pk_Tc
165
Agc_Pk
165
Agc Targets
165
Agc Noise Parameters
166
10 Spi Commands
166
Audio Play and Record Commands
169
Play Voice Prompt
170
Play Voice Prompt @Rn, N = 0 ~ 7
170
Play Voice Prompt, Loop
170
Play Voice Prompt, Loop, @Rn, N = 0 ~ 7
172
Stop Loop-Play Command
172
Execute Voice Macro
172
Execute Voice Macro @Rn, N = 0 ~ 7
173
Record Message
173
Record Message at Address
174
Play Message at Address
174
Play Silence
175
Stop Command
175
Erase Message at Address
176
SPI Send Audio Data
176
SPI Receive Audio Data
177
SPI Send Compressed Audio Data for Direct Programming to Flash
179
SPI Receive Previous REC_MSG or REC_MSG@ Compressed Audio Data Stored in Flash
180
SPI Send Compressed Data to Decode
181
SPI Receive Encoded Data
182
Device Status Commands
183
Read Status
183
Read Interrupt
183
Read Recorded Message Address Details
183
Read Message Length
184
Read ISD61S00 ID
184
Digital Memory Commands
185
Digital Read
185
Digital Write
185
Erase Memory
186
Chip Erase
186
Checksum
187
Device Configuration Commands
187
PWR_UP - Power up
188
PWR_DN - Power down
188
WR_CFG_REG - Write Configuration Register
188
RD_CFG_REG - Read Configuration Register
188
Device Power up Sequence
189
11 Isd61S00 Memory Management
189
ISD61S00 Memory Format
189
Message Management
190
Voice Prompts
191
Voice Macros
191
User Data
192
Reserved Sectors
192
Message Recordings
192
Memory and Message Headers
193
Memory Header
193
Message Header
194
Digital Access of Memory
194
Device Erase Commands
195
Memory Contents Protection
195
12 Device Initialization
195
13 Application Reference Schematics
196
PCB Layout Guidelines
196
14 Package Specification
199
LQFP48L (7X7X1.4Mm Footprint 2.0Mm)
199
15 Electrical Characteristics
200
Absolute Maximum Ratings
200
Operating Conditions
200
DC Parameters
201
Analog Transmission Characteristics
202
Analog Distortion and Noise Parameters
202
8Khz Sampling
202
16Khz Sampling
203
SPI Timing
203
Recommended Clock/Crystal Specification
204
Dual Tone Alert Signal (CAS)
205
FSK Detection - 1200Baud Bell 202, ITU V.23, 300 Baud Bell 103, ITU V.21
206
FSK Transmitter - Bell 202, ITU-V.23, Bell 103, ITU-V.21
208
DTMF Detection
209
16 Ordering Information
210
17 Revision History
211
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