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6.4.6
Register Description
CONFIG0 (Address =
0x0030_0000)
31
30
CWDTEN[2]
23
22
CBOV
15
14
Reserved
7
6
CBS
Bits
Descriptions
[31]
CWDTEN[2]
[30:28]
Reserved
CFGXT1
[27]
[26]
CFOSC
[25:24]
Reserved
CBOV
[23:21]
Sep 9, 2019
ISD94100 Series Technical Reference Manual
29
28
Reserved
21
20
CBORST
CBODEN
13
12
GPA8_LOW
5
4
Reserved
CWDTE[1:0]
Watchdog Timer Hardware Enable Bit
When watchdog timer hardware enable function is enabled, the watchdog enable bit
WDTEN (WDT_CTL[7]) and watchdog reset enable bit RSTEN (WDT_CTL[1]) is set to 1
automatically after power on. The clock source of watchdog timer is forced to LIRC and LIRC
can't be disabled.
CWDTEN[2:0] is CONFIG0[31][4][3],
111 = WDT hardware enable function is inactive.
Others = WDT hardware enable function is active. WDT clock is always on.
Reserved bit should always be programmed with 1.
XTAL Multi-Function Select
0 = XTAL pins are configured as GPIO pins.
1 = XTAL pins are configured as external 4~24.576 MHz external high speed crystal
oscillator (HXT) pins.
CPU Clock Source Selection After Reset
The value of CFOSC will be loaded to HCLK (CLK_CLKSEL0[2:0]) in system clock controller
after any reset occurs. HCLK[2:0] = 111 if CFOSC = 1, HCLK[2:0] = 000 if CFGSC=0.
0 = External high speed crystal oscillator (HXT)
1 = Internal high speed RC oscillator (HIRC)
Reserved bit should always be programmed with 1.
Brown-Out Voltage Selection
000 = Brown-out voltage is 1.6V.
001 = Brown-out voltage is 1.8V.
010 = Brown-out voltage is 2.0V.
011 = Brown-out voltage is 2.2V.
100 = Brown-out voltage is 2.4V.
101 = Brown-out voltage is 2.6V.
110 = Brown-out voltage is 2.8V.
111 = Brown-out voltage is 3.0V.
Page 217 of 928
27
26
CFGXT1
CFOSC
19
18
Reserved
11
10
CIOINI
3
2
LOCK2
25
24
Reserved
17
16
9
8
Reserved
1
0
LOCK
DFEN
Rev1.09
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