Figure 6.8-31 Brake Block Diagram For Pwm0_Ch0 And Pwm0_Ch1 Pair - Nuvoton ISD94124BYI Technical Reference Manual

Edge Detect
Brake Source
Level Detect
Brake Source
BRKESTS1(PWM_INTSTS1[17])

Figure 6.8-31 Brake Block Diagram for PWM0_CH0 and PWM0_CH1 Pair

Figure 6.8-32 illustrates the edge detector waveform for PWM0_CH0 and PWM0_CH1 pair. In this
case, the edge detect brake source has occurred twice for the brake events. When the event occurs,
both of the BRKEIF0 and BRKEIF1 flags are set and BRKESTS0 and BRKESTS1 bits are also set
to indicate brake state of PWM0_CH0 and PWM0_CH1. For the first occurring event, software
writes 1 to clear the BRKEIF0 flag. After that, the BRKESTS0 bit is cleared by hardware at the next
start of the PWM period. At the same moment, the PWM0_CH0 outputs the normal waveform even
though the brake event is still occurring. The second event also triggers the same flags, but at this
time, software writes 1 to clear the BRKEIF1 flag. Afterward, PWM0_CH1 outputs normally at the
next start of the PWM period.
As a contrast to the edge detector example, Figure 6.8-33 illustrates the level detector waveform
for PWM0_CH0 and PWM0_CH1 pair. In this case, the BRKLIF0 and BRKLIF1 flags can only
indicate the brake event having occurred. The BRKLSTS0 and BRKLSTS1 brake states will
automatically recover at the start of the next PWM period no matter at what states the BRKLIF0
and BRKLIF1 flags are at that moment.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
BRKEIF0 or BRKEIF1 (PWM_INTSTS1[1:0])
BRKEIEN0_1 (PWM_INTEN1[0])
BRKLIF0 or BRKLIF1
(PWM_INTSTS1[9:8])
BRKLIEN0_1 (PWM_INTEN1[8])
BRKLSTS0 (PWM_INTSTS1[24])
BRKESTS0
(PWM_INTSTS1[16])
Low level
detection
BRKLSTS1(PWM_INTSTS1[25])
Page 429 of 928
Edge Detect
Brake Interrupt
Level Detect
Brake Interrupt
(PWM_BRKCTL0[17:16])
(PWM_BRKCTL0[19:18])
Note: denotes falling edge detect
BRK_INT
BRKAEVEN
PWM_OUT0
PWM_OUT1
BRKAODD
Rev1.09