Figure 6.14-25 Tx Underflow Event And Slave Under Run Event; Figure 6.14-26 Two-Bit Transfer Mode Fifo Buffer Example (Spi0 Only); Figure 6.14-27 Tx Underflow Event (Spi0 Slave 3-Wire Mode Enabled) - Nuvoton ISD94124BYI Technical Reference Manual

Figure 6.14-25 TX Underflow Event and Slave Under Run Event

In 2-Bit Transfer mode, the transmit data is loaded into shift register after 2 datum have been written
into the TX FIFO buffer. It uses two shift registers and two 4-level skew buffers concurrently. The
detail timing of 2-Bit Transfer mode, please refer to the section of Two-Bit Transfer mode.
Example :
SPI0
TWOBIT = 1
DWIDTH =0
LSB = 1
TX Skew Buffer
TX Shift Register
TX Buffer
TXEMPTY = 1

Figure 6.14-26 Two-Bit Transfer Mode FIFO Buffer Example (SPI0 Only)

In SPI0 Slave 3-Wire mode, the first 2-bit data is un-predicted (keep on the level of last bit in
previously transfer) if the data is written into TX FIFO among 3 peripheral clock cycles before the
SPI bus clock is presented. The other bits are held by TXUFPOL (SPI0_FIFOCTL[6]) because there
is TX underflow event. The written data will be transmitted in the next transfer.
Less than 3 slave
peripheral clock cycles
SPI0_CLK
TXEMPTY
TXUFIF
SPI0_MISO0

Figure 6.14-27 TX Underflow Event (SPI0 Slave 3-Wire Mode Enabled)

In Slave mode, during receiving operation, the serial data is received from SPI0_MOSI0 and
SPIx_MOSI (x=1, 2) pin and stored to SPIn_RX register. The reception mechanism is similar to
Sep 9, 2019
ISD94100 Series Technical Reference Manual
H/W load TX
Write
Buffer into
2 Data
Shift Register
Data 1
Data 0
TXEMPTY = 0
1st transaction word
Data 0 is written into TX FIFO Buffer among 3 peripheral
clock cycles before SPI bus clock is presented
Unknown TXUFPOL
Page 696 of 928
SPI0_MOSI0
b2
b1
b0
Data1 Data1
b31|b30...b1|b0 0 0 b31...b4|b3
Data0 Data0
b31|b30...b1|b0 0 0 b31...b4|b3
H/W load Shift
Register into
Skew Buffer
TXEMPTY = 1 TXEMPTY = 1
Data 0
SPI0_MOSI1
b2
b1
b0
Rev1.09