Table 6.4.4-4 Fmc Control Registers For Flash Read/Write - Nuvoton ISD94124BYI Technical Reference Manual

period; the peripheral still keeps working as usual. If any interrupt request occurs, CPU will not
service it until ISP operation is finished. When ISP operation is finished, the ISPGO bit will be cleared
by hardware automatically. Software can poll ISPGO bit to determine whether ISP operation is
finished.
ISP operation status is presented in FMC_ISPSTS register. Software can check the status and do
the corresponding error handling if necessary. Particularly, if ISPFF (FMC_ISPSTS[6])=1, it means
ISP is actually not started and error handling is desired.
6.4.4.5 Flash Read and write Operations
The ISD94100 series supports 32-bit and 64-bit read operations. Programming wise the ISD94100
series supports 32-bit, 64-bit and multi-word flash write operations.
Table 6.4.4-4 below gives a quick reference for the registers involved in each one of the above
operations. Before any read or write operation, the ISPEN bit in FMC_ISPCTRL register needs to
be enabled; and after operation finishes, ISPEN bit needs to be disabled for the purpose of data
security. For more detailed information about these registers, please refer to Register Description
section.
Register Description
FMC_ISPCTL ISP Control Register
FMC_ISPADDR ISP Address Register
FMC_ISPDAT ISP Data Register
FMC_ISPCMD ISP Command Register
FMC_ISPTRG ISP Trigger Register
FMC_ISPSTS ISP Status Register
FMC_MPDAT0 ISP Data0 Register
FMC_MPDAT1 ISP Data1 Register
FMC_MPDAT2 ISP Data2 Register
FMC_MPDAT3 ISP Data3 Register
FMC_MPSTA ISP Multi-Program status
FMC_MPADDR ISP Multi-Program Address

Table 6.4.4-4 FMC control registers for Flash Read/Write

6.4.4.5.1 Read Operations
The ISD94100 series supports two kinds of flash reads: 32-bit read and 64-bit read. Please note for
the purpose of data integrity, the user needs to set ISPEN bit in FMC->ISPCTL register before flash
read/write operation, and clear ISPEN bit after the operation is completed.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
32-Bit
Read/Write


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Read: 0x00
Write: 0x21
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N/A
N/A
N/A
N/A
N/A
N/A
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64-Bit Multi-Word
Read/Write Write
 
 
N/A N/A
Read: 0x40
0x27
Write: 0x61
 

N/A
 
 

N/A

N/A

N/A

N/A
Rev1.09