Figure 6.14-24 Receive Fifo Buffer Example - Nuvoton ISD94124BYI Technical Reference Manual

RX Skew Buffer
RX Shift Register
Example 1
SPI0
RX FIFO Buffer
DWIDTH =0
LSB = 1
Example 2 RX Shift Register
SPI0
DWIDTH =0
RX FIFO Buffer
LSB = 1
In Slave mode, during transmission operation, when data is written to the SPIn_TX register by
software, the data will be loaded into transmit FIFO buffer and the TXEMPTY (SPIn_STATUS[16])
will be set to 0. The transmission will start when the slave device receives clock signal from master.
Data can be written to SPIn_TX register as long as the TXFULL (SPIn_STATUS[17]) is 0. After all
data have been drawn out by the SPI transmission logic unit and the SPIn_TX register is not
updated by software, the TXEMPTY (SPIn_STATUS[16]) will be set to 1.
If there is no any data written to the SPIn_TX register, the transmit underflow interrupt flag, TXUFIF
(SPIn_STATUS[19]) will be set to 1 when the slave selection signal is active. The output data will
be held by TXUFPOL (SPIn_FIFOCTL[6]) setting during this transfer until the slave selection signal
goes to inactive state. When the transmit underflow event occurs, the slave under run interrupt flag,
SLVURIF (SPIn_STATUS[7]), will be set to 1 as slave selection pin goes to inactive state.
SPIx_SSy pin
SPIx_CLK pin
TXEMPTY
TXUFIF
SPIx_MISOz pin
SLVURIF
Note:
x: Controller number (x = 0, 1, 2), y: Slave selection pin channel number in SPI0 (y = 0, 1),
z: MOSI and MISO pin channel number in SPI0 (z = 0)
Sep 9, 2019
ISD94100 Series Technical Reference Manual
b0 b1
................b0
H/W Load
Skew Buffer
into Shift
Register
RXEMPTY = 1 RXEMPTY = 1
1. H/W load
Shift Register
b31|b30...b1|b0 Data 1
into RX FIFO
2. H/W Load
Skew Buffer
into Shift
Register
Data 0
RXEMPTY = 1 RXEMPTY = 0

Figure 6.14-24 Receive FIFO Buffer Example

TXUFPOL
Page 695 of 928
b32
1. H/W load Shift
Register into RX
b31|b30...b1|b0
FIFO
2. H/W Load
H/W Load 32
Skew Buffer into
bits into
Shift Register
Shift Register
RXEMPTY = 1
th
1. Read Out by
The 9
Data 9
User
can not load
2. Repeat
into RX FIFO
Data 8
Data 7
Receive Data
Buffer when
Data 6
into RX FIFO
RX FIFO Full
Data 5
Data 4
Data 3
Data 2
Data 1
RXEMPTY = 0
RXFULL = 1
Data 0 is written
into FIFO Buffer
Data 0
Read & Clear by
User
b33
..............b32
Data 0
RXEMPTY = 0
Data
Data N
Data 8
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
RXEMPTY = 0
RXFULL = 1
RXOVIF = 1
Rev1.09