Block Diagram; Figure 6.14-1 Spi Block Diagram (Spi0); Figure 6.14-2 Spi Block Diagram (Spi1/2) - Nuvoton ISD94124BYI Technical Reference Manual

6.14.3 Block Diagram

DMA
Interface
Control
Peripheral clock
APB
Interface
Control
8-Level TX
FIFO Buffer
8-Level RX
FIFO Buffer
Note: SPI0_MOSI1 and SPI0_MISO1 are only available in 2-Bit Transfer mode or Quad I/O mode
DMA
Interface
Control
Peripheral clock
Status / Control
Registers
APB
Interface
Control
4-Level TX
FIFO Buffer
4-Level RX
FIFO Buffer
Sep 9, 2019
ISD94100 Series Technical Reference Manual
Core Logic
Status / Control
Registers
TX Shift
Register
RX Shift
Register

Figure 6.14-1 SPI Block Diagram (SPI0)

Core Logic
TX Shift
Register
RX Shift
Register

Figure 6.14-2 SPI Block Diagram (SPI1/2)

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SPI0_SS1
4-Bit
Skew
Buffer
4-Bit
Skew
Buffer
SPIx_I2SMCLK
SPIx_CLK (I2Sn_BCLK)
SPIx_SS (I2Sn_LRCLK)
SPIx_MOSI (I2Sn_DO)
4-Bit
Skew
Buffer
4-Bit
SPIx_MISO (I2Sn_DI)
Skew
Buffer
Note: x = 1, 2
SPI0_CLK
SPI0_SS0
SPI0_MOSI0
SPI0_MOSI1
SPI0_MISO0
SPI0_MISO1
Rev1.09