User Manuals: Nuvoton ISD91200 Series Security System

Manuals and User Guides for Nuvoton ISD91200 Series Security System. We have 1 Nuvoton ISD91200 Series Security System manual available for free PDF download: Technical Reference Manual

Nuvoton ISD91200 Series Technical Reference Manual

Nuvoton ISD91200 Series Technical Reference Manual (473 pages)

Brand: Nuvoton | Category: Single board computers | Size: 4 MB

Table of Contents

Table of Contents

2
1 General Description

11
2 Features

12
3 Part Information and Pin Configuration

16
- Pin Configuration
  16
- Pin Description
  17
4 Block Diagram

22
5 Functional Description

23
- ARM ® Cortex™-M0 Core
  23
- System Manager
  25
  - Overview
    25
  - System Reset
    25
  - System Power Distribution
    26
  - System Memory Map
    27
  - System Manager Control Registers
    29
  - System Timer (Systick)
    53
  - Nested Vectored Interrupt Controller (NVIC)
    57
  - System Control Registers
    103
- Clock Controller and Power Management Unit (PMU)
  111
  - Clock Generator
    111
  - System Clock & Systick Clock
    112
  - Peripheral Clocks
    113
  - Power Management
    113
  - Register Map
    115
  - Register Description
    116
- General Purpose I/O
  133
  - Overview and Features
    133
  - GPIO I/O Modes
    133
  - GPIO Control Register Map
    135
  - Register Description
    136
- Brownout Detection and Temperature Alarm
  146
  - Brownout Register Map
    146
  - Brownout Register Description
    147
- I2C Serial Interface Controller (Master/Slave)
  150
  - Introduction
    150
  - Modes of Operation
    154
  - Data Transfer Flow in Five Operating Modes
    155
  - I2C Protocol Registers
    161
  - Register Mapping
    164
  - Register Description
    165
- PWM Generator and Capture Timer
  172
  - Introduction
    172
  - Features
    172
  - PWM Generator Architecture
    174
  - PWM-Timer Operation
    174
  - PWM Double Buffering, Auto-Reload and One-Shot Operation
    176
  - Modulate Duty Cycle
    176
  - Dead-Zone Generator
    177
  - Capture Timer Operation
    178
  - PWM-Timer Interrupt Architecture
    179
  - PWM-Timer Initialization Procedure
    179
  - PWM-Timer Stop Procedure
    179
  - Capture Start Procedure
    180
  - Register Map
    181
  - Register Description
    183
- Real Time Clock (RTC) Overview
  200
  - RTC Features
    200
  - RTC Block Diagram
    201
  - RTC Function Description
    201
  - Register Map
    204
  - Register Description
    205
- Serial 0 Peripheral Interface (SPI0) Controller
  218
  - Overview
    218
  - Features
    218
  - SPI0 Block Diagram
    218
  - SPI0 Function Descriptions
    219
  - SPI Timing Diagram
    229
  - SPI Configuration Examples
    232
  - Register Map
    234
  - Register Description
    235
- Serial 1 Peripheral Interface (SPI1) Controller
  250
  - Overview
    250
  - Features
    250
  - SPI1 Block Diagram
    250
  - SPI1 Function Descriptions
    251
  - SPI Timing Diagram
    257
  - SPI Configuration Examples
    260
  - Register Map
    262
  - Register Description
    263
- Timer Controller
  274
  - General Timer Controller
    274
  - Features
    274
  - Timer Controller Block Diagram
    274
  - Register Map
    275
  - Register Description
    276
- Watchdog Timer
  281
  - Register Map
    283
  - Register Description
    284
- UART Interface Controller
  286
  - Overview
    286
  - Features of UART Controller
    288
  - Block Diagram
    289
  - Irda Mode
    291
  - LIN (Local Interconnection Network) Mode
    293
  - Register Map
    294
  - Register Description
    295
- I2S Audio PCM Controller
  314
  - Overview
    314
  - Features
    314
  - I2S Block Diagram
    315
  - I2S Operation
    316
  - FIFO Operation
    317
  - Register Map
    318
  - Register Description
    319
- PDMA Controller
  330
  - Overview
    330
  - Features
    330
  - Block Diagram
    330
  - Function Description
    331
  - Register Map
    332
  - Register Description
    333
- Volume Control
  352
  - Overview and Feature
    352
  - Volume Control Register Map
    352
  - Volume Control Register Description
    353
6 Flash Memory Controller (Fmc)

356
- Overview
  356
- Features
  356
- Flash Memory Controller Block Diagram
  357
- Flash Memory Organization
  358
- Boot Selection
  358
- Data Flash (DATAF)
  359
- User Configuration (CONFIG)
  360
- In-System Programming (ISP)
  362
  - ISP Procedure
    362
- Register Map
  365
- Register Description
  366
7 Analog Signal Path Blocks

373
- Sigma- Delta Analog-To-Digital Converter (SDADC)
  373
  - Functional Description
    373
  - Features
    373
  - Block Diagram
    373
  - Operation
    374
  - ADC Register Map
    379
  - ADC Register Description
    380
- Bridge Sense
  390
  - Functional Description
    390
  - Features
    390
  - Block Diagram
    390
  - Operation
    391
  - Register Map
    392
  - Register Description
    393
- Audio Class D Speaker Driver (DPWM)
  398
  - Functional Description
    398
  - Features
    398
  - Block Diagram
    398
  - Operation
    398
  - DPWM Register Map
    401
  - DPWM Register Description
    402
- Analog Functional Blocks
  408
  - Overview
    408
  - Features
    408
  - Register Map
    408
  - VMID Reference Voltage Generation
    409
  - LDO Power Domain Control
    410
  - Microphone Bias (Replaced by Bridge Sense ADC)
    412
  - Oscillator Frequency Measurement and Control
    413
- Automatic Level Control (ALC)
  419
  - Overview and Features
    419
  - Register Map
    423
  - Register Description
    424
- Capacitive Sensing Scan (CSCAN) and Operational Amplifiers
  430
  - Overview and Features
    430
  - Features
    430
  - Operation
    430
  - Operational Amplifier
    430
  - Comparator
    433
  - Register Map
    433
  - Register Description
    434
- Biquad Filter (BIQ)
  442
  - Overview and Features
    442
  - Register Map
    443
  - Register Description
    445
- Successive Approximation Analog-To-Digital Convertor (SARADC)
  450
  - Overview and Features
    450
  - Block Diagram
    451
  - Function Description
    451
  - Register Map
    457
  - Register Description
    458
8 Application Diagram

468
9 Package Dimensions

469
- LQFP (7X7X1.4Mm Footprint 2.0Mm)
  469
- QFN 32L 4X4 Mm2, Thickness: 0.8Mm (Max), Pitch: 0.40Mm
  470

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