Figure 6.8-34 Brake Source Block Diagram; Figure 6.8-35 Brake System Fail Block Diagram - Nuvoton ISD94124BYI Technical Reference Manual

shown in Figure 6.8-34.
Among the above described brake sources, the brake source coming from system fail can still be
specified to several different system fail conditions. These conditions include clock fail, Brown-out
detect, SRAM parity check error and Core lockup. Figure 6.8-35 shows that by setting
corresponding enable bits, the enabled system fail condition can be one of the sources to issue the
Brake system fail to the PWM brake.
PWM0_BRAKE0
PWM0_BRAKE1
CSSBRKEN (PWM_FAILBRK[0])
BODBRKEN (PWM_FAILBRK[1])
RAMBRKEN (PWM_FAILBRK[2])
CORBRKEN (PWM_FAILBRK[3])
6.8.5.24 Polarity Control
Each PWM port, from PWM_CH0 to PWM_CH5, has an independent polarity control module to
configure the polarity of the active state of the PWM output. By default, the PWM output is active
high. This implies the PWM OFF state is low and ON state is high. This definition is variable through
setting the PWM Negative Polarity Control Register (PWM_POLCTL), for each individual PWM
channel. Figure 6.8-36 shows the initial state before PWM starting with different polarity settings.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
Brake Noise Filter
BRKP0EEN (PWM_BRKCTL0[4])
Brake Noise Filter
BRKP1EEN (PWM_BRKCTL0[5])
EADCEBEN (PWM_BRKCTL0[20])
Brake System Fail
SYSEBEN (PWM_BRKCTL0[7])
BRKETRG0 (PWM_SWBRK[0])
Brake Noise Filter
BRKP0LEN (PWM_BRKCTL0[12])
Brake Noise Filter
BRKP1LEN (PWM_BRKCTL0[13])
EADCLBEN (PWM_BRKCTL0[28])
Brake System Fail
SYSLBEN (PWM_BRKCTL0[15])
BRKLTRG0 (PWM_SWBRK[8])

Figure 6.8-34 Brake Source Block Diagram

Clock Fail
Brown-Out Detect
SRAM Parity Error
Core Lockup

Figure 6.8-35 Brake System Fail Block Diagram

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Edge Detect
Brake Source
EADCRM
Level Detect
Brake Source
EADCRM
Brake System
Fail
Brake Source
Brake
Function
Brake
Function
Rev1.09