Figure 6.3-1 Clock Generator Global View Diagram - Nuvoton ISD94124BYI Technical Reference Manual

HIRC HXT
48 / 49.152 4~24.576
MHz MHz
HIRC
1
HXT
0
CLK_PLLCTL[19]
HIRC
111
LIRC
011
PLLFOUT
010
LXT
001
HXT
000
CLK_CLKSEL0[2:0]
LIRC
11
HCLK
1/2048 10
LXT
01
CLK_CLKSEL1[1:0]
LIRC
11
HCLK
1/2048 10
CLK_CLKSEL1[31:30]
HIRC
1/2 111
HCLK
1/2 011
HXT
1/2 010
LXT
001
HXT
000
CLK_CLKSEL0[5:3]
LIRC
1
LXT
0
CLK_CLKSEL3[8]
HIRC
11
PCLK0
10
PLLFOUT
01
HXT
00
CLK_CLKSEL2[3:2]
CLK_CLKSEL2[7:6]
HIRC
111
LIRC
101
TM0/TM1 011
PCLK0
010
LXT
001
HXT
000
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
HIRC
11
PCLK1
10
PLLFOUT
01
HXT
00
CLK_CLKSEL2[11:10]
HIRC
11
PCLK0
10
PLLFOUT
01
HXT
00
CLK_CLKSEL3[17:16]

Figure 6.3-1 Clock Generator Global View Diagram

Sep 9, 2019
ISD94100 Series Technical Reference Manual
LXT LIRC
CPU
32.768 10
kHz kHz
CRC
FMC
PDMA
PLLFOUT
PLL FOUT SRAM
HCLK
1/(HCLKDIV+1)
WDT
WWDT
CPUCLK
1
SysTick
0
SYST_CTRL[2]
CLK_CLKSEL1[29:28]
RTC
SPI0
1/(SPI0_CLKDIV[8:0]+1)
1/(SPI2_CLKDIV[8:0]+1)
SPI2
TMR0
TMR1
DMIC
PLLFOUT
HIRC
I2S
CLK_CLKSEL4[24]
Page 141 of 928
PWM0
I2C0
SPI0
PCLK0
/1,/2,/4,/8,/16 SPI2
TMR0
TMR1
I2S
DPWM
/1,/2,/4,/8,/16
PCLK1
1/(EADCDIV+1) EADC
PCLK0
1
PWM 0
PLLFOUT
0
CLK_CLKSEL2[0]
HIRC
11
LXT
10
1/(UART0DIV+1)
PLLFOUT
01
HXT
00
CLK_CLKSEL1[25:24]
DIV1EN
HIRC (CLK_CLKOCTL[5])
11
HCLK
10
(CLK_CLKOCTL[3:0]+1)
/2
LXT
01
HXT
00
LIRC
/10000 1
1 Hz clock from RTC
LXT
/32768 0
RTCSEL(CLK_CLKSEL3[8])
HIRC
11
PCLK1
10
1/(SPI1_CLKDIV[8:0]+1)
PLLFOUT
01
HXT
00
CLK_CLKSEL2[5:4]
HIRC
111
LIRC
101
011
TM2/TM3
TMR2
PCLK1
010 TMR3
LXT
001
HXT
000
CLK_CLKSEL1 [18:16]
CLK_CLKSEL1[22:20]
HIRC
11
PCLK0
10
DPWM
PLLFOUT
01
HXT
00
CLK_CLKSEL2[13:12]
1
48MHz
/(USBDIV + 1) /4
0
EADC
I2C1
RTC
PCLK1
SPI1
TMR2
TMR3
DMIC
UART0
CLK1HZEN
(CLK_CLKOCTL[6])
0
0
CLKO
1
1
SPI1
USB1.1 PHY
USB1.1 Device
Controller
Rev1.09