Figure 6.20-2 Vad Clock Control Diagram - Nuvoton ISD94124BYI Technical Reference Manual

HIRC
11
PCLK1
10
PLLFOUT
01
HXT
00
ACTIVE
D
(VAD_STATUS0[31])
ACTCL
(VAD_SINCCTL[30])
VADEN
(VAD_SINCCTL[31])
CHEN0
(DMIC_CTL[0])
SW
(VAD_SINCCTL[29])
6.20.5.2 VAD Data Control
The VAD data diagram is shown in Figure 6.20-3.
When VAD enabled (VADEN (VAD_SINCCTL[31]) = 1) and voice detected (ACTIVE
(VAD_STATUS0[31]) = 1), the PCM data can be sent to SRAM via PDMA to do key word detection
by software solution. And user can stop sending PCM data to SRAM by setting register DATAOFF
(VAD_SINCCTL[28]).
SINC
DMIC_IN (CH0)
ACTIVE
D Q
(VAD_STATUS0[31])
ACTCL
(VAD_SINCCTL[30])
VADEN
(VAD_SINCCTL[31])
CHEN0
(DMIC_CTL[0])
ACTCL (VAD_SINCCTL[30])
SW
(VAD_SINCCTL[29])
Sep 9, 2019
ISD94100 Series Technical Reference Manual
1/(1+PCLKDIV)
DMICCKEN
(CLK_APBCLK0[15])
Q
ACTCL (VAD_SINCCTL[30])

Figure 6.20-2 VAD Clock Control Diagram

Biquad
SINC
Page 880 of 928
DMIC Path
(DMIC_CLK)
DMIC_MCLK
1/(1+MCLKDIV)
1/4
VAD Path
(VAD_CLK)
D Q
Note:
PCLKDIV = DMIC_DIV[7:0]
MCLKDIV = DMIC_DIV[15:8]
VAD Path
VAD
0
[15:0]
FIFO
DMIC
1
[23:0]
DMIC Path
D Q
Note:
X: Data output always be 0
1
DMIC_CLK
0
0
PDMA
1
X
DATAOFF
(VAD_SINCCTL[28])
Rev1.09