Register Description - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc
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6.6.7

Register Description

Descriptor Table Control Register
(PDMA_DSCTn_CTL)
Offset
Register
PDMA_DSCT0_CTL
PDMA_BA + 0x00
PDMA_DSCT1_CTL
PDMA_BA + 0x10
PDMA_DSCT2_CTL
PDMA_BA + 0x20
PDMA_DSCT3_CTL
PDMA_BA + 0x30
PDMA_DSCT4_CTL
PDMA_BA + 0x40
PDMA_DSCT5_CTL
PDMA_BA + 0x50
PDMA_DSCT6_CTL
PDMA_BA + 0x60
PDMA_DSCT7_CTL
PDMA_BA + 0x70
PDMA_DSCT8_CTL
PDMA_BA + 0x80
PDMA_DSCT9_CTL
PDMA_BA + 0x90
PDMA_DSCT10_CTL PDMA_BA + 0xA0
PDMA_DSCT11_CTL PDMA_BA + 0xB0
PDMA_DSCT12_CTL PDMA_BA + 0xC0
PDMA_DSCT13_CTL PDMA_BA + 0xD0
PDMA_DSCT14_CTL PDMA_BA + 0xE0
PDMA_DSCT15_CTL PDMA_BA + 0xF0
31
30
23
22
15
14
STRIDEEN
Reserved
7
6
TBINTDIS
Description
Bits
[31:16]
TXCNT
Sep 9, 2019
ISD94100 Series Technical Reference Manual
R/W Description
R/W Descriptor Table Control Register of PDMA Channel 0
R/W Descriptor Table Control Register of PDMA Channel 1
R/W Descriptor Table Control Register of PDMA Channel 2
R/W Descriptor Table Control Register of PDMA Channel 3
R/W Descriptor Table Control Register of PDMA Channel 4
R/W Descriptor Table Control Register of PDMA Channel 5
R/W Descriptor Table Control Register of PDMA Channel 6
R/W Descriptor Table Control Register of PDMA Channel 7
R/W Descriptor Table Control Register of PDMA Channel 8
R/W Descriptor Table Control Register of PDMA Channel 9
R/W Descriptor Table Control Register of PDMA Channel 10
R/W Descriptor Table Control Register of PDMA Channel 11
R/W Descriptor Table Control Register of PDMA Channel 12
R/W Descriptor Table Control Register of PDMA Channel 13
R/W Descriptor Table Control Register of PDMA Channel 14
R/W Descriptor Table Control Register of PDMA Channel 15
29
28
TXCNT
21
20
TXCNT
13
12
TXWIDTH
5
4
BURSIZE
Reserved
Transfer Count
The TXCNT represents the required number of PDMA transfer, the real transfer count is
(TXCNT + 1); The maximum transfer count is 65536, every transfer may be byte, half-word
or word that is dependent on TXWIDTH field.
Page 278 of 928
27
26
25
19
18
17
11
10
9
DAINC
3
2
1
TXTYPE
Reset Value
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
24
16
8
SAINC
0
OPMODE
Rev1.09

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