Figure 6.14-12 Byte Reorder Function; Figure 6.14-13 Timing Waveform For Byte Suspend - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc

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SPI_TX/SPI_RX

In Master mode, if REORDER (SPIn_CTL[19]) is set to 1, a suspend interval of 0.5 ~ 15.5 SPI clock

periods will be inserted by hardware between two successive bytes in a transaction word. The

suspend interval is configured in SUSPITV (SPIn_CTL[7:4]).

SPIx_CLK pin

SPIx_MOSIz pin

SPIx_MISOz pin

Timing Condition is CLKPOL = 0, LSB = 0, TXNEG = 1, DWIDTH = 0, REORDER = 1 and SLAVE = 0

x: Controller number (x = 0, 1, 2), z: MOSI and MISO pin channel number in SPI0 (z = 0, 1)

6.14.5.4 Half-Duplex Communication

The SPI controller can communicate in half-duplex mode by setting HALFDPX (SPIn_CTL[14]) bit.

In half-duplex mode, there is only one data line for receiving or transmitting data direction which is

defined by DATDIR (SPIn_CTL[20]). In half-duplex configuration, the SPI0_MISO0 and SPIx_MISO

(x=1, 2) pin is free for other applications and it can be configured as GPIO. Enabling or disabling

the control bit HALFDPX (SPIn_CTL[14]) will produce TXRST (SPIn_FIFOCTL[1]) and RXRST

(SPIn_FIFOCTL[0]) at the same time automatically.

ISD94100 Series Technical Reference Manual

LSB = 0 (MSB first)

& REORDER = 1

Figure 6.14-12 Byte Reorder Function

1st Transaction Byte

Page 686 of 928

TX/RX FIFO Buffer

Byte0 Byte1 Byte2

x = unknown byte

TX[15] TX[14]

2nd Transaction Byte

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