Figure 6.13-27 I 2 C Time-Out Count Block Diagram - Nuvoton ISD94124BYI Technical Reference Manual

time-out counter. User may write 1 to clear TOIF to 0.
Pclk 0
1
1/4
DIV4
I2CEN
INTEN
6.13.5.4.8 Wake-up Control Register (I2C_WKCTL)
When chip enters Power-down mode and set WKEN (I2C_WKCTL [0]) to 1, other I
wake up our chip by addressing our I
entering sleep mode. The ACK bit cycle of address match frame is done in power-down. The
controller will stretch the SCL to low when the address is matched the device's address and the
ACK cycle done, then I
controller will don't stretch the SCL to low. Notice that when the controller don't stretch the SCL to
low, transmit or receive data will perform immediately. If data transmitted or received when SI event
is not clear, user must reset I
6.13.5.4.9 Wake-up Status Register (I2C_WKSTS)
When system is woken up by other I
write "1" to clear this bit.
When the chip is woken-up by address match with one of the device address register (I2C_ADDRn),
the user shall check the WKAKDONE (I2C_WKSTS [1]) bit is set to 1 to confirm the address byte
has done. The WKAKDONE bit indicates that the ACK bit cycle of address byte is done in power-
down. The controller will stretch the SCL to low when the address is matched the device's slave
address and the ACK cycle done. The SCL is stretched until WKAKDONE is clear by user. If the
frequency of SCL is low speed and the system has wakeup from address match frame, the user
shall check WKAKDONE to confirm this frame has transaction done and then to do the wakeup
procedure. Notice that user can't release WKIF through clearing the WKAKDONE bit to 0.
The WRSTSWK (I2C_WKSTS [2]) bit records the Read/Write command before the I
send address. The user can read this bit's status to prepare the next transmitted data (WRSTSWK
= 0) or to wait the incoming data (WRSTSWK = 1) can be stored in time after the system is wake-
up by the address match frame. Notice that the WRSTSWK (I2C_WKSTS [2]) bit is cleared when
write one to the WKAKDONE (I2C_WKSTS [1]) bit.
When system is woken up by other I
write "1" to clear this bit.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
14-bits Counter
Enable
SI
Figure 6.13-27 I 2 C Time-out Count Block Diagram
2
C device, user must configure the related setting before
2
C controller will go ahead. If NHDBUSEN (I2C_WKCTL [7]) is set, the
2
C controller and execute the original operation again.
2
C master device, WKIF is set to indicate this event. User needs
2
C master device, WKIF is set to indicate this event. User needs
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TIF
Clear Counter
SI
To I2C Interrupt
2
C master can
2 C controller
Rev1.09