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6.3.7
Clock Setting Limitation
The maximum frequency of PCLK0 and PCLK1 is 90 MHz. If the frequency of HCLK greater than
90 MHz, the APB1DIV (CLK_PCLKDIV[6:4]) and APB0DIV(CLK_PCLKDIV[2:0]) must be set to the
appropriate value to keep the PCLK0 and PCLK1 less than or equal to 90MHz.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
Page 146 of 928
Rev1.09
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