Register Map - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc
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6.6.6

Register Map

R: read only, W: write only, R/W: both read and write
Offset
Register
PDMA Base Address:
PDMA_BA = 0x4000_8000
PDMA_DSCT0_CTL
PDMA_BA + 0x00
PDMA_DSCT0_SA
PDMA_BA + 0x04
PDMA_DSCT0_DA
PDMA_BA + 0x08
PDMA_DSCT0_NEXT
PDMA_BA + 0x0C
PDMA_DSCT1_CTL
PDMA_BA + 0x10
PDMA_DSCT1_SA
PDMA_BA + 0x14
PDMA_DSCT1_DA
PDMA_BA + 0x18
PDMA_DSCT1_NEXT
PDMA_BA + 0x1C
PDMA_DSCT2_CTL
PDMA_BA + 0x20
PDMA_DSCT2_SA
PDMA_BA + 0x24
PDMA_DSCT2_DA
PDMA_BA + 0x28
PDMA_DSCT2_NEXT
PDMA_BA + 0x2C
PDMA_DSCT3_CTL
PDMA_BA + 0x30
PDMA_DSCT3_SA
PDMA_BA + 0x34
PDMA_DSCT3_DA
PDMA_BA + 0x38
PDMA_DSCT3_NEXT
PDMA_BA + 0x3C
PDMA_DSCT4_CTL
PDMA_BA + 0x40
PDMA_DSCT4_SA
PDMA_BA + 0x44
PDMA_DSCT4_DA
PDMA_BA + 0x48
PDMA_DSCT4_NEXT
PDMA_BA + 0x4C
PDMA_DSCT5_CTL
PDMA_BA + 0x50
PDMA_DSCT5_SA
PDMA_BA + 0x54
PDMA_DSCT5_DA
PDMA_BA + 0x58
PDMA_DSCT5_NEXT
PDMA_BA + 0x5C
Sep 9, 2019
ISD94100 Series Technical Reference Manual
R/W Description
R/W Descriptor Table Control Register of PDMA Channel 0 0xXXXX_XXXX
R/W Source Address Register of PDMA Channel 0
R/W Destination Address Register of PDMA Channel 0
First Scatter-Gather Descriptor Table Offset Address of
R/W
PDMA Channel 0
R/W Descriptor Table Control Register of PDMA Channel 1 0xXXXX_XXXX
R/W Source Address Register of PDMA Channel 1
R/W Destination Address Register of PDMA Channel 1
First Scatter-Gather Descriptor Table Offset Address of
R/W
PDMA Channel 1
R/W Descriptor Table Control Register of PDMA Channel 2 0xXXXX_XXXX
R/W Source Address Register of PDMA Channel 2
R/W Destination Address Register of PDMA Channel 2
First Scatter-Gather Descriptor Table Offset Address of
R/W
PDMA Channel 2
R/W Descriptor Table Control Register of PDMA Channel 3 0xXXXX_XXXX
R/W Source Address Register of PDMA Channel 3
R/W Destination Address Register of PDMA Channel 3
First Scatter-Gather Descriptor Table Offset Address of
R/W
PDMA Channel 3
R/W Descriptor Table Control Register of PDMA Channel 4 0xXXXX_XXXX
R/W Source Address Register of PDMA Channel 4
R/W Destination Address Register of PDMA Channel 4
First Scatter-Gather Descriptor Table Offset Address of
R/W
PDMA Channel 4
R/W Descriptor Table Control Register of PDMA Channel 5 0xXXXX_XXXX
R/W Source Address Register of PDMA Channel 5
R/W Destination Address Register of PDMA Channel 5
First Scatter-Gather Descriptor Table Offset Address of
R/W
PDMA Channel 5
Page 273 of 928
Reset Value
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
Rev1.09

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