Figure 6.19-5 Dmic Fifo Contents For Various Settings - Nuvoton ISD94124BYI Technical Reference Manual

DMIC_CTL[9:8] = 00, DMIC_CTL[3:0] = 0001
Redundant bits
DMIC_CTL[9:8] = 10, DMIC_CTL[3:0] = 1000
Redundant bits
DMIC_CTL[9:8] = 00, DMIC_CTL[3:0] = 0011
Redundant bits
Redundant bits
DMIC_CTL[9:8] = 10, DMIC_CTL[3:0] = 1100
Redundant bits
Redundant bits
DMIC_CTL[9:8] = 11, DMIC_CTL[3:0] = 1111
Redundant bits
Redundant bits
Redundant bits
Redundant bits
DMIC_CTL[9:8] = 00, DMIC_CTL[3:0] = 1111
Redundant bits
Redundant bits
Redundant bits
Redundant bits

Figure 6.19-5 DMIC FIFO Contents for Various Settings

6.19.5.6 Peripheral DMA Request
Normal use of the DMIC is with PDMA. In this mode DMIC requests PDMA service whenever there
is space in FIFO. PDMA channel will copy data from a streaming buffer to the DMIC and alert the
CPU when buffer is empty. In this way an entire buffer of data can be sent to DMIC without any
CPU intervention.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
Data on Falling Clock Edge of DMIC_DAT0 pin
23
Data on Falling Clock Edge of DMIC_DAT1 pin
23
Data on Falling Clock Edge of DMIC_DAT0 pin
23
Data on Rising Clock Edge of DMIC_DAT0 pin
23
Data on Rising Clock Edge of DMIC_DAT1 pin
23
Data on Falling Clock Edge of DMIC_DAT1 pin
23
Data on Rising Clock Edge of DMIC_DAT0 pin
23
Data on Falling Clock Edge of DMIC_DAT0 pin
23
Data on Rising Clock Edge of DMIC_DAT1 pin
23
Data on Falling Clock Edge of DMIC_DAT1 pin
23
Data on Falling Clock Edge of DMIC_DAT0 pin
23
Data on Rising Clock Edge of DMIC_DAT0 pin
23
Data on Falling Clock Edge of DMIC_DAT1 pin
23
Data on Rising Clock Edge of DMIC_DAT1 pin
23
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N
0
N
0
N
0
N+1
0
N
0
N+1
0
N
0
N+1
0
N+2
0
N+3
0
N
0
N+1
0
N+2
0
N+3
0
Rev1.09