Figure 6.14-36 Spi Timing In Master Mode (Alternate Phase Of Spix_Clk); Figure 6.14-37 Spi Timing In Slave Mode; Figure 6.14-38 Spi Timing In Slave Mode (Alternate Phase Of Spix_Clk) - Nuvoton ISD94124BYI Technical Reference Manual

Figure 6.14-36 SPI Timing in Master Mode (Alternate Phase of SPIx_CLK)

SSACTPOL=1
SPIx_SSy pin
SSACTPOL=0
CLKPOL=0
SPIx_CLK pin
CLKPOL=1
SPIx_MISOz pin
SPIx_MOSIz pin
Note:
Slave Mode
Registers Setting: SLAVE=1, LSB=0, DWIDTH=0x08
CLKPOL=0, TXNEG=1, RXNEG=0 or CLKPOL=1, TXNEG=0, RXNEG=1
x: Set number (x = 0, 1, 2), y: Slave select channel number in SPI0 (y = 0, 1),
z: MOSI and MISO channel number in SPI0 (z = 0)
SSACTPOL=1
SPIx_SSy pin
SSACTPOL=0
CLKPOL=0
SPIx_CLK pin
CLKPOL=1
SPIx_MISOz pin
SPIx_MOSIz pin
Note:
Slave Mode
Registers Setting: SLAVE=1, LSB=1, DWIDTH=0x08
CLKPOL=0, TXNEG=0, RXNEG=1 or CLKPOL=1, TXNEG=1, RXNEG=0
x: Set number (x = 0, 1, 2), y: Slave select channel number in SPI0 (y = 0, 1),
z: MOSI and MISO channel number in SPI0 (z = 0)

Figure 6.14-38 SPI Timing in Slave Mode (Alternate Phase of SPIx_CLK)

Sep 9, 2019
ISD94100 Series Technical Reference Manual
MSB
TX[6] TX[0]
TX[7]
MSB
RX[6] RX[0]
RX[7]

Figure 6.14-37 SPI Timing in Slave Mode

LSB
TX[1]
TX[0]
LSB
RX[1]
RX[0]
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TX[7] TX[6]
RX[7] RX[6]
TX[7] TX[0] TX[1]
RX[7] RX[0] RX[1]
LSB
TX[0]
LSB
RX[0]
MSB
TX[7]
MSB
RX[7]
Rev1.09