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CPU, via user code present in
APROM/LDROM, can
erase/program/read flash memory via
ISP registers, can modify registers and
SRAM
Accept ICP mass erase command
SWD/ICE can use page
erase/program/read flash memory by ICP
SWD/ICE can use page
erase/program/read flash memory via ISP
registers, can modify registers and SRAM
CortexM4 ICE can set breakpoints, read
registers
Table 6.4.4-6 The lock effect table with two protections
Sep 9, 2019
ISD94100 Series Technical Reference Manual
LOCK2, LOCK (CONFIG0[2:1])
11
10
YES
YES
YES
YES
YES
Page 214 of 928
01
00
YES
YES
YES
YES
YES
YES
NO
YES
NO
NO
NO
NO
YES
NO
NO
Rev1.09
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