Figure 6.13-2 I2C Bus Timing; Figure 6.13-3 I 2 C Protocol - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc

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line may be changed only during the low period of SCL and must be held stable during the high

period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START

or STOP). Please refer to the Figure 6.13-2 for more detailed I

The device's on-chip I

specification. The I

C port handles byte transfers autonomously. To enable this port, the bit I2CEN

in I2C_CTL should be set to '1'. The I

SCL. When I/O pins are used as I

Note: Pull-up resistor is needed for I

Figure 6.13-3 shows the typical I

session consists of four stages:

START or Repeated START condition

Slave address and R/W bit transfer

Data transfer

STOP condition

6.13.5.1.1 START or Repeated START signal

When the bus is free/idle, which means no master device is engaging the bus (both SCL and SDA

lines are high), a master can initiate a new I2C session by generating a START condition. A START

condition, usually referred to as the "S" bit, is defined as a HIGH to LOW transition on the SDA line

while SCL is HIGH. The START condition denotes the beginning of a new data transmission.

After a successful data transmitting /receiving session, a master can generate a STOP condition to

release the I2C bus, or generate a Repeated START (Sr) condition for continuing data transfer. The

ISD94100 Series Technical Reference Manual

Figure 6.13-2 I2C Bus Timing

C provides the serial interface that meets the I

C hardware interfaces to the I

C ports, user must set the pins function to I

C operation as the SDA and SCL are open-drain pins.

C signal waveform. Normally, a standard I2C communication

Figure 6.13-3 I

Page 620 of 928

C BUS Timing.

C bus standard mode

C bus via two pins: SDA and

C in advance.

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