Functional Description - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc

Table of Contents

6.13.4.2 I2C1 Basic Configurations

Clock source configuration

Enable I2C1 peripheral clock in I2C1CKEN (CLK_APBCLK0[9]).

Reset configuration

Reset I2C1 controller in I2C1RST (SYS_IPRST1[9]).

Pin configuration

6.13.5 Functional Description

C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and

SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit long. There is one

SCL clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit

follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA

ISD94100 Series Technical Reference Manual

Page 619 of 928

Show Quick Links

Table of Contents