Figure 6.4-10 Flash 64-Bit Write Procedure - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc
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Code snippet for 32_bit flash write:
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPCTL &= ~(7<<8);
FMC->ISPADDR = u32Addr;
FMC->ISPDAT = u32Data;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
// Check ISPFF flag (FMC_ISPCTL[6])
64-bit Write
Figure 6.4-10 illustrates the operation flow of 64-bit flash write. Two data registers are involved:
FMC_MPDAT0 for LSB word, and FMC_MPDAT1 for MSB word. The ISP command is 0x61.
Enable ISPEN
Write FMC_ISPADDR
Write FMC_ISPCMD
Write FMC_MPDAT0
Write FMC_MPDAT1
Set ISPGO = 1
Check ISPGO = 0
YES
Sample code for 64_bit flash write:
FMC->ISPCMD = FMC_ISPCMD_PROGRAM_64;
FMC->ISPCTL |= (3<<8);
FMC->ISPADDR = u32addr;
FMC->MPDAT0 = u32data0;
FMC->MPDAT1 = u32data1;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) ;
FMC->ISPCTL &= ~(7<<8);
// Check ISPFF flag(FMC_ISPCTL[6])
...
Multi-word Write
The ISD94100 series supports Multi-word Write function to speed up flash programming. Each one
Sep 9, 2019
ISD94100 Series Technical Reference Manual
// op code for 32-bit write is 0x21
// Set PT = 0
Start
Set PT
NO
?

Figure 6.4-10 Flash 64-bit write procedure

//extend programming pulse
Page 204 of 928
End of Flash Operation
Check ISPFF = 1?
End of ISP
NO
Operation
?
YES
Stop
// op code for 64-bit write is 0x61
Rev1.09

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