Figure 6.12-12 Uart Ncts Auto-Flow Control Enabled; Figure 6.12-13 Uart Nrts Auto-Flow Control Enabled - Nuvoton ISD94124BYI Technical Reference Manual

UART0_nCTS pin input status of UART function mode
CTSSTS
(UART_MODEMSTS[4])
UART0_nCTS pin
input
MODEMINT interrupt
CTSDETF
UART0_TXD pin
output

Figure 6.12-12 UART nCTS Auto-Flow Control Enabled

As shown in Figure 6.12-13, in UART nRTS auto-flow control mode (ATORTSEN
(UART_INTEN[12])=1), the nRTS internal signal is controlled by UART FIFO controller with
RTSTRGLV(UART_FIFO[19:16]) trigger level.
Setting RTSACTLV (UART_MODEM[9]) can control the nRTS pin output is inverse or non-inverse
from nRTS signal. User can read the RTSSTS (UART_MODEM[13]) bit to get real nRTS pin output
voltage logic status.
UART0_nRTS pin output status of UART function mode, nRTS auto - flow control enabled
The Bytes
Number Stored
In FIFO
nRTS Signal
(internal signal)
RTSACTLV = 0
RTSSTS
(UART_MODEM[13])
UART0_nRTS pin
RTSACTLV = 1
output
(Default)
UART0_RXD pin
input
(from external)

Figure 6.12-13 UART nRTS Auto-Flow Control Enabled

As shown in Figure 6.12-14, in software mode (ATORTSEN(UART_INTEN[12])=0), the nRTS flow
Sep 9, 2019
ISD94100 Series Technical Reference Manual
CTSACTLV=0
Active
CTSACTLV=1
(default)
MODEMINT interrupt
Clear by softwave
Start
Idle D0
bit
TX output
delay
RTSTRGLV
<
(UART_FIFO[19:16])
Start
Byte(i)
bit
External
delay
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Inactive
Clear by softwave
D1 D2 D3 D4 D5 D6 D7
The Bytes Number
Stored In FIFO
Active
Start
Byte (i +n)
bit
nRTS inactive
TX stop
Stop
P Idle
bit
RTSTRGLV
=
(UART_FIFO[19:16])
delay
Rev1.09