Features; Isd94100 Series Features - Nuvoton ISD94124BYI Technical Reference Manual

2

FEATURES

2.1

ISD94100 Series Features

 Core
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®
ARM Cortex
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Supports DSP extension with hardware divider
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Supports IEEE 754 compliant Floating-point Unit (FPU)
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Supports Memory Protection Unit (MPU)
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One 24-bit system timer
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Supports Low Power Sleepmode by WFI and WFE instructions
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Single-cycle 32-bit hardware multiplier
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Supports programmable 16 level priorities of Nested Vectored Interrupt Controller
(NVIC)
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Supports programmable mask-able interrupts
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Supports Embedded Trace Macrocell
 Built-in LDO for wide operating voltage range
 Flash Memory
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Up to 512KB on-chip Application ROM (APROM)
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Configurable program code/data allocation
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4 KB Flash for loader (LDROM)
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Supports 2-wire ICP update through SWD/ICE interface
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Supports In-system program (ISP), In application program (IAP) update
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Supports 4 KB page erase for all embedded flash
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Supports 4 KB two-way cache to reduce power consumption and improve
performance.
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Enhanced performance up to 3.4 Core Mark/MHz when running code in Flash with
cache
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Supports 2-wire ICP flash updating through SWD interface
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Supports 32-bit/64-bit and multi-word flash programming function.
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Supports fast flash programming verification by CRC function.
 SRAM
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Up to 192 KB embedded SRAM
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32 KB SRAM in bank 0 that supports hardware parity check and retention mode
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Supports byte-, half-word- and word-access
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Supports exception (NMI) generated once a parity check error occurs
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Supports PDMA mode
 Clock Control
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Built-in 48.0 MHz or 49.152 MHz selectable internal high speed RC oscillator (HIRC) for
system operation
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Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-
up operation
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4~24.576 MHz external high speed crystal oscillator (HXT) for precise timing operation
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32.768 kHz external low speed crystal oscillator (LXT) for RTC function and low-power
Sep 9, 2019
ISD94100 Series Technical Reference Manual
®
-M4F core running up to 200 MHz
Page 19 of 928 Rev1.09