Register Description - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc

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Register Description

WDT Control Register

ISD94100 Series Technical Reference Manual

R/W Description

R/W WDT Control Register

ICE Debug Mode Acknowledge Disable Control (Write Protected)

0 = ICE debug mode acknowledgement affects WDT counting.

WDT up counter will be held while CPU is held by ICE.

1 = ICE debug mode acknowledgement Disabled.

WDT up counter will keep going no matter CPU is held by ICE or not.

Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Reserved. Any values read should be ignored. When writing to this field always write

with reset value.

WDT Time-out Interval Selection (Write Protected)

These three bits select the time-out interval period for the WDT.

Note: This bit is write protected. Refer to the SYS_REGLCTL register.

WDT Enable Control (Write Protected)

0 = WDT Disabled (This action will reset the internal up counter value).

1 = WDT Enabled.

Note1: This bit is write protected. Refer to the SYS_REGLCTL register.

Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not

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