Register Description - Nuvoton ISD94124BYI Technical Reference Manual

6.17.7 Register Description

I2S Control Register 0 (I2S_CTL0)
Register Offset
I2S_CTL0 I2S_BA+0x00
31 30
TDMCHNUM
23 22
RXLCH Reserved
15 14
MCLKEN
7 6
ORDER MONO
Bits Description
[31:30] TDMCHNUM
[29:28] CHWIDTH
[27] PCMSYNC
Sep 9, 2019
ISD94100 Series Technical Reference Manual
R/W Description
2
R/W I S Control Register 0
29 28
CHWIDTH
21 20
RXPDMAEN TXPDMAEN
13 12
Reserved
5 4
DATWIDTH
TDM Channel Number
This bit fields are used to define the TDM channel number in one audio frame while PCM
mode (FORMAT[2] = 1).
00 = 2 channels in audio frame.
01 = 4 channels in audio frame.
10 = 6 channels in audio frame.
11 = 8 channels in audio frame.
Channel Width
This bit fields are used to define the length of audio channel. If CHWIDTH < DATWIDTH,
the hardware will set the real channel length as the bit-width of audio data which is defined
by DATWIDTH.
00 = The bit-width of each audio channel is 8-bit.
01 = The bit-width of each audio channel is 16-bit.
10 = The bit-width of each audio channel is 24-bit.
11 = The bit-width of each audio channel is 32-bit.
PCM Synchronization Pulse Length Selection
This bit field is used to select the high pulse length of frame synchronization signal in PCM
protocol
0 = One BCLK period.
1 = One channel period.
Note: This bit is only available in master mode
Page 815 of 928
27 26
PCMSYNC
19 18
RXFBCLR TXFBCLR FLZCDEN
11 10
3 2
MUTE RXEN
Reset Value
0x0000_0000
25 24
FORMAT
17 16
FRZCDEN
9 8
SLAVE
1 0
TXEN I2SEN
Rev1.09