Figure 6.12-5 Uart Ncts Wake-Up Case1; Figure 6.12-6 Uart Ncts Wake-Up Case2 - Nuvoton ISD94124BYI Technical Reference Manual

nCTS Wake-up Case 1 (nCTS transition from low to high)
HCLK
nCTS
CTSWKF
Note: Stable count means HCLK source recovery stable count.
nCTS Wake-up Case 2 (nCTS transition from high to low)
HCLK
nCTS
CTSWKF
Note: Stable count means HCLK source recovery stable count.
Incoming data wake-up:
When system is in Power-down mode and the WKDATEN (UART_WKCTL [1]) is set, toggling on
incoming data (UART0_RXD) pin wakes up the system, and DATWKF (UART_WKSTS[1]) will be
set to 1.
In order to correctly receive the incoming data after system wake-up, the Start bit Compensation
Value STCOMP (UART_DWKCOMP[15:0]) shall be set in advance. STCOMP bits indicate how
many UART0_CLK cycles the UART controller can have to become stable and be ready to receive
1 st bit (start bit) after wakeup.
Note1: The UART controller clock source should be selected from HIRC and the compensation
time for start bit is about 15.68us. It means that the value of STCOMP (UART_DWKCOMP[15:0])
can be set as 347.
Note2: The value
(UART_DWKCOMP[15:0]).
Sep 9, 2019
ISD94100 Series Technical Reference Manual
Power-down mode
CTSACTLV (UART_MODEMSTS[8]) = 0

Figure 6.12-5 UART nCTS Wake-up Case1

Power-down mode
CTSACTLV (UART_MODEM[8]) = 1

Figure 6.12-6 UART nCTS Wake-up Case2

of BRD(UART_BAUD[15:0])
Page 576 of 928
CPU run
stable count
CPU run
stable count
should be greater than STCOMP
Rev1.09