Register Map - Nuvoton ISD94124BYI Technical Reference Manual

6.2.10 Register Map

R: read only, W: write only, R/W: both read and write
Offset
Register
SYS Base Address:
SYS_BA = 0x4000_0000
SYS_PDID
SYS_BA+0x00
SYS_RSTSTS SYS_BA+0x04
SYS_IPRST0
SYS_BA+0x08
SYS_IPRST1 SYS_BA+0x0C
SYS_IPRST2
SYS_BA+0x10
SYS_BODCTL SYS_BA+0x18
SYS_PORCTL
SYS_BA+0x24
SYS_USBPHY SYS_BA+0x2C
SYS_GPA_MFPL
SYS_BA+0x30
SYS_GPA_MFPH SYS_BA+0x34
SYS_GPB_MFPL SYS_BA+0x38
SYS_GPB_MFPH SYS_BA+0x3C
SYS_GPC_MFPL SYS_BA+0x40
SYS_GPC_MFPH SYS_BA+0x44
SYS_GPD_MFPL SYS_BA+0x48
SYS_GPD_MFPH SYS_BA+0x4C
SYS_SRAM_INTCTL SYS_BA+0xC0
SYS_SRAM_STATUS SYS_BA+0xC4
SYS_SRAM_ERRADDR SYS_BA+0xC8
SYS_IRCTCTL SYS_BA+0xF0
SYS_IRCTIEN SYS_BA+0xF4
SYS_IRCTISTS SYS_BA+0xF8
SYS_REGLCTL SYS_BA+0x100
SYS_RCADJ SYS_BA+0x110
Note:
1. Any register not listed here is reserved and must not be written. The result of a read operation on these bits is undefined.
2. The reserved register fields that listed in register description must be written to their reset value. Writing reserved fields with
other than reset values may produce undefined results.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
R/W Description
R Part Device Identification Number Register
R/W System Reset Status Register
R/W Peripheral Reset Control Register 0
R/W Peripheral Reset Control Register 1
R/W Peripheral Reset Control Register 2
R/W Brown-Out Detector Control Register
R/W Power-On-Reset Controller Register
R/W USB PHY Control Register
R/W GPIOA Low Byte Multiple Function Control Register
R/W GPIOA High Byte Multiple Function Control Register 0x0000_0000
R/W GPIOB Low Byte Multiple Function Control Register 0x0110_0000
R/W GPIOB High Byte Multiple Function Control Register 0x0000_0000
R/W GPIOC Low Byte Multiple Function Control Register 0x0000_0000
R/W GPIOC High Byte Multiple Function Control Register 0x0000_0000
R/W GPIOD Low Byte Multiple Function Control Register 0x0000_0000
R/W GPIOD High Byte Multiple Function Control Register 0x0000_0011
R/W System SRAM Interrupt Enable Control Register
R/W System SRAM Parity Error Status Register
R System SRAM Parity Check Error Address Register
R/W HIRC Trim Control Register
R/W HIRC Trim Interrupt Enable Register
R/W HIRC Trim Interrupt Status Register
R/W Register Lock Control Register
R/W HIRC Trim Value Register
Page 66 of 928
Reset Value
[1]
0x1DXX_05XX
0x0000_0043
0x0000_0000
0x0000_0000
0x0000_0000
0x000X_038X
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0XXX
Rev1.09