Register Description - Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc

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6.21.7 Register Description

DPWM Control Register (DPWM_CTL)

DPWM_BA+0x00

ISD94100 Series Technical Reference Manual

R/W Description

R/W DPWM Control Register

Working Clock Selection

0 = 512 fs working clock

1 = 500 fs working clock

Note: For example, if the user want to get 48 kHz sample rate (fs), the frequency of

DPWM_CLK need to be 24576 kHz when CLKSET = 0, the frequency of DPWM_CLK need

to be 24000 kHz when CLKSET = 1.

Reserved. Any values read should be ignored. When writing to this field always write with

reset value.

11 = Clear the FIFO.

Others = Reserved. Do not use.

Note 1: To clear the FIFO, need to write FCLR (DPWM_CTL[29:28]) to 11b, and can read

the EMPTY (DPWM_STATUS[1]) bit to make sure that the FIFO has been cleared.

Note 2: This field is auto cleared by hardware.

BIQ Band Number Setting (Total 10 Bands)

This field represents the required number of bands. The minimum number is 1 and can up

to 10 when user enables biquad filter or splitter.

Reserved. Any values read should be ignored. When writing to this field always write with

reset value.

Splitter Enable Bit

0 = 4-band splitter Disabled.

1 = 4-band splitter Enabled.

Note: Splitter shared biquad filter 4 bands, the minimum number of BIQBANDNUM is 4, if

splitter is enabled.

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