Table 6.4.4-1 Flash Memory Address Map - Nuvoton ISD94124BYI Technical Reference Manual

LDROM
LDROM is designed for a loader to implement In-System-Programming (ISP) function. It is a 4 KB
size flash memory region, the range of address from 0x0010_0000 to 0x0010_0FFF.
Configuration Bytes
The ISD94100 device provides 3-words of flash memory, from address 0x0030_0000 to store
system configuration such as logic, flash security lock, boot select, brown-out voltage level, Data
Flash base address, etc. The configuration bytes take effect after system reset.
User can call normal FMC single word read function to read these configuration bytes. To update
these configuration bytes, user shall first set CFGUEN bit in FMC_ISPCTL register, and then call
FMC Erase followed by FMC Write function to complete the update.
Refer to Table CONFIG0, CONFIG1 and CONFIG2 in Register Description section for details of the
configuration bits.
Block Name
APROM
Data Flash
LDROM
User
Configuration
Note: N is the page number of configured data flash. One page size is 4096 bytes, N >= 0
6.4.4.2 Boot Configuration
Typically the system vector table is located in ROM space from 0x0000_0000 to 0x0000_01FF.
When the processor exits from reset, it loads the MSP (Main Stack Pointer) from address
0x0000_0000, and loads the PC counter with the value pointed of the RESET Vector, which is stored
at address 0x0000_0004. The processor then starts to fetch code from the address pointed to by
the RESET vector and program execution begins.
The ISD94100 device has the capability of mapping vector table into APROM space from
0x0000_0000 to 0x0000_01FF, or into LDROM space from 0x0010_0000 to 0x0010_01FF. Thus
provides the flexibly of booting from APROM or from LDROM.
The ISD94100 device supports In Application Programming (IAP) function that the device can
update its own firmware when it is running. By booting into IAP mode, without JTAG involved, the
device can re-program other parts of the ROM (APROM, LDROM or Data Flash). Under IAP mode
the ISD94100 series device supports remapping function. That is, (typically after IAP programming
is finished) the MCU can issue re-mapping to dynamically change the data and code read access,
so that the MCU can switch execution from LDROM, APROM or SRAM.
Through CBS[1:0] bits in CONFIG0, the ISD94100 series offers four boot configurations, as shown
in Table 6.4.4-2.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
Size Start Address
(512-4*N) KB 0x0000_0000
4*N KB DFBADR
(if DFEN=0) (if DFEN=0)
4 KB 0x0010_0000
3 words 0x0030_0000

Table 6.4.4-1 Flash Memory Address Map

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End Address
0x0007_FFFF(512 KB, if DFEN=1)
DFBADR-1 (if DFEN=0)
0x0007_FFFF (512 Kbytes)
0x0010_0FFF
0x0030_000B
Rev1.09