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Nuvoton ISD94124BYI Technical Reference Manual

Isd arm cortex-m4f soc
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ISD94100 Series Technical Reference Manual
®
®
ISD ARM
Cortex
-M4F SoC
ISD94100 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of microcontroller based system design.
Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Sep 9, 2019
Page 1 of 928
Rev1.09

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Summary of Contents for Nuvoton ISD94124BYI

  • Page 1 The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.

  • Page 2: Table Of Contents

    ISD94100 Series Technical Reference Manual TABLE OF CONTENTS GENERAL DESCRIPTION ............18 FEATURES ................19 ISD94100 Series Features ..............19 ABBREVIATIONS ............... 26 Abbreviations ................26 PARTS INFORMATION LIST AND PIN CONFIGURATION ..... 28 Parts Information ................28 Ordering Information ............... 29 Pin Configuration ................
  • Page 3 ISD94100 Series Technical Reference Manual System Control Register ..............131 6.2.14 Clock Controller ................140 Overview ................... 140 6.3.1 Clock Generator ................... 142 6.3.2 System Clock and SysTick Clock .............. 143 6.3.3 Peripheral Clock .................. 145 6.3.4 Power-down Mode Clock ................ 145 6.3.5 Clock Output ..................
  • Page 4 ISD94100 Series Technical Reference Manual Overview ................... 338 6.7.1 Features .................... 338 6.7.2 Block Diagram ..................340 6.7.3 Basic Configuration ................344 6.7.4 Timer Functional Description ..............345 6.7.5 PWM Functional Description ..............350 6.7.6 Register Map ..................363 6.7.7 Register Description ................
  • Page 5 ISD94100 Series Technical Reference Manual Block Diagram .................. 545 6.11.3 Basic Configuration ................545 6.11.4 Functional Description ................. 545 6.11.5 Register Map..................549 6.11.6 Register Description ................550 6.11.7 UART Interface Controller (UART) ............566 6.12 Overview ..................566 6.12.1 Features ..................
  • Page 6 ISD94100 Series Technical Reference Manual Basic Configuration ................747 6.15.4 Functional Description ................. 747 6.15.5 Register Map..................749 6.15.6 Register Description ................750 6.15.7 Enhanced 12-bit Analog-to-Digital Converter (EADC) ....... 755 6.16 Overview ..................755 6.16.1 Features ..................755 6.16.2 Block Diagram ..................
  • Page 7 ISD94100 Series Technical Reference Manual Register Description ................872 6.19.7 Voice Active Detection (VAD) ............879 6.20 Overview ..................879 6.20.1 Features ..................879 6.20.2 Block Diagram .................. 879 6.20.3 Basic Configuration ................879 6.20.4 Functional Description ................. 879 6.20.5 Register Map..................
  • Page 8 ISD94100 Series Technical Reference Manual List of Figure Figure 4.2-1 Ordering Information Scheme ................... 29 Figure 4.3-1 QFN48 (6x6 mm) Pin Diagram .................. 31 Figure 4.3-2 LQFP64 (7x7 mm) Pin Diagram ................32 Figure 4.3-3 LQFP64 (10x10 mm) Pin Diagram ................33 Figure 5.1-1 ISD94100 Series Block Diagram ................
  • Page 9 ISD94100 Series Technical Reference Manual Figure 6.4-17 Flash access cycle auto-tuning flow ..............213 Figure 6.5-1 GPIO Controller Block Diagram ................241 Figure 6.5-2 Push-Pull Output ...................... 242 Figure 6.5-3 Open-Drain Output ....................243 Figure 6.5-4 Quasi-Bidirectional I/O Mode ................... 243 Figure 6.5-5 GPIO Rising Edge Trigger Interrupt ................
  • Page 10 ISD94100 Series Technical Reference Manual Figure 6.7-23 PWM 0% to 100% Duty Cycle in Up Count Type and Up-Down Count Type ..357 Figure 6.7-24 PWM Independent Mode Output Waveform ............358 Figure 6.7-25 PWM Complementary Mode Output Waveform ............ 358 Figure 6.7-26 PWMx_CH0 Output Control in Independent Mode ..........
  • Page 11 ISD94100 Series Technical Reference Manual Figure 6.8-28 Dead-Time Insertion ....................427 Figure 6.8-29 Illustration of Mask Control Waveform ..............427 Figure 6.8-30 Brake Noise Filter Block Diagram ................428 Figure 6.8-31 Brake Block Diagram for PWM0_CH0 and PWM0_CH1 Pair ....... 429 Figure 6.8-32 Edge Detector Waveform for PWM0_CH0 and PWM0_CH1 Pair ......
  • Page 12 ISD94100 Series Technical Reference Manual Figure 6.12-13 UART nRTS Auto-Flow Control Enabled ............583 Figure 6.12-14 UART nRTS Auto-Flow with Software Control ............ 584 Figure 6.12-15 RS-485 nRTS Driving Level in Auto Direction Mode ........... 586 Figure 6.12-16 RS-485 nRTS Driving Level with Software Control ..........586 Figure 6.12-17 Structure of RS-485 Frame .................
  • Page 13 ISD94100 Series Technical Reference Manual Table 6.14-3 SPI/I2S Interface Controller Pin Description (SPI1~SPI2) ........680 Figure 6.14-4 SPI Peripheral Clock ....................680 Figure 6.14-5 SPI0 Full-Duplex Master Mode Application Block Diagram ........681 Figure 6.14-6 SPI0 Full-Duplex Slave Mode Application Block Diagram ........681 Figure 6.14-7 SPI1 ~ SPI2 Full-Duplex Master Mode Application Block Diagram ......
  • Page 14 ISD94100 Series Technical Reference Manual Figure 6.15-2 CHECKSUM Bit Order Reverse Functional Block ..........748 Figure 6.15-3 Write Data Bit Order Reverse Functional Block ............ 748 Figure 6.16-1 ADC Converter Block Diagram ................756 Figure 6.16-2 Sample Module 0~3 Block Diagram ..............758 Figure 6.16-3 Sample Module 4~12 Block Diagram ..............
  • Page 15 ISD94100 Series Technical Reference Manual Figure 6.17-15 TDM 6-channel audio format with 24-bit data in 32-bit channel block (PCM with LSB justified; FORMAT=0x6)......................807 Figure 6.17-16 I S Interrupts ......................809 Figure 6.17-17 FIFO Contents for Various 2-channel Audio Modes ..........810 Figure 6.17-18 FIFO Contents for Various 4-channel Audio Modes ..........
  • Page 16 ISD94100 Series Technical Reference Manual List of Tables Table 3.1-1 List of Abbreviations ....................27 Table 4.1-1 Devices Features and Peripheral Counts ..............28 Table 4.2-1 Devices Features Summary ..................30 Table 4.4-1 Pin Description ......................42 Table 4.5-1 GPIO Alternate Function Summary ................44 Table 6.2.2-1 Reset Value of Registers ..................
  • Page 17 ISD94100 Series Technical Reference Manual Table 6.10.5-2 CMPDAT Setting Limitation ................. 537 Table 6.11.5-1 RTC Read/Write Enable ..................546 Table 6.11.5-2 12/24 hour Time Scale Selection ................. 547 Table 6.11.5-3 Registers value after power-on ................548 Table 6.12.2-1 UART Feature ...................... 567 Table 6.12.3-1 UART Interrupt .....................

  • Page 18: General Description

    ISD94100 Series Technical Reference Manual GENERAL DESCRIPTION ® ® The ISD94100 series 32-bit microcontrollers are an embedded ARM Cortex -M4F core with DSP extensions and a Floating Point Unit which run up to 200 MHz. It provides up to 512 KB of flash memory and up to 192 KB of SRAM.

  • Page 19: Features

    ISD94100 Series Technical Reference Manual FEATURES ISD94100 Series Features  Core – ® ® Cortex -M4F core running up to 200 MHz – Supports DSP extension with hardware divider – Supports IEEE 754 compliant Floating-point Unit (FPU) – Supports Memory Protection Unit (MPU) –...
  • Page 20 ISD94100 Series Technical Reference Manual system operation – Supports one PLL up to 500 MHz for high performance system operation, sourced from HIRC or HXT – Supports clock failure detection for high/low speed external crystal oscillator – Supports exception (NMI) generation once a clock failure detected –...
  • Page 21 ISD94100 Series Technical Reference Manual  Supports independent mode for PWM output channel  Supports 8 channel PWM outputs in complementary mode  Supports mask function and tri-state enable for each PWM pin  Supports interrupt on the following events: ...
  • Page 22 ISD94100 Series Technical Reference Manual – Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second – Supports 1 Hz, clock output – Supports wake-up from idle mode, Power-down mode and Standby Power-down mode –...
  • Page 23 ISD94100 Series Technical Reference Manual – Supports multi-address Power-down wake-up function  I – Supports one I S interface – Interface with external audio CODEC – Supports Master and Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes –...
  • Page 24 ISD94100 Series Technical Reference Manual – I2S supports Master and Slave mode – I2S supports 8-, 16-, 24- and 32-bit audio data sizes – I2S supports mono and stereo audio data – I2S supports PCM mode A, PCM mode B, I2S and MSB justified data format –...
  • Page 25 ISD94100 Series Technical Reference Manual – Supports PDMA transfer. – Supports up to four channel digital microphones. – Both digital PDM microphone inputs can be used simultaneously.  Voice Active Detection – Configuration detect levels. – Supports idle mode wake-up function. –...

  • Page 26: Abbreviations

    ISD94100 Series Technical Reference Manual ABBREVIATIONS Abbreviations Description Acronym ACMP Analog Comparator Controller Analog-to-Digital Converter Advanced Encryption Standard Advanced Peripheral Bus Advanced High-Performance Bus Brown-out Detection Controller Area Network Debug Access Port Data Encryption Standard DMIC Digital Microphone Inputs DPWM Audio DPWM Modulator External Bus Interface EPWM...

  • Page 27: Table 3.1-1 List Of Abbreviations

    ISD94100 Series Technical Reference Manual Pulse Width Modulation Quadrature Encoder Interface Secure Digital Serial Peripheral Interface Samples per Second TDES Triple Data Encryption Standard Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID Universal Serial Bus Voice Active Detection Watchdog Timer WWDT Window Watchdog Timer...

  • Page 28: Parts Information List And Pin Configuration

    ISD94100 Series Technical Reference Manual PARTS INFORMATION LIST AND PIN CONFIGURATION Parts Information ISD941 PART NUMBER Max. CPU frequency (MHz) Flash (KB) SRAM (KB) ISP Loader ROM (KB) 32-bit Timer √ UART SPI/I √ USB 1.1 FS Device 12-bit ADC Audio DPWM √...

  • Page 29: Ordering Information

    ISD94100 Series Technical Reference Manual Ordering Information I9 4 X X X X X ISD Audio Product Family Product Series 4: Cortex-M4F Family ID 1: Family Series ID Flash ROM 1: 256KB 2: 512KB SRAM Size 3: 128KB 4: 192KB Feature A: Standard B: Basic, no Audio...

  • Page 30: Table 4.2-1 Devices Features Summary

    ISD94100 Series Technical Reference Manual PART NUMBER FLASH FEATURE PACKAGE ISD94124BYI 192 KB 512 KB Basic feature QFN48 (6x6 mm) 128 KB 512 KB Basic feature QFN48 (6x6 mm) ISD94123BYI 128 KB 256 KB Basic feature QFN48 (6x6 mm) ISD94113BYI...

  • Page 31: Pin Configuration

    ISD94100 Series Technical Reference Manual Pin Configuration 4.3.1 QFN48 (6x6 mm) Pin Diagram PA.4 PD.1 Top transparent view PA.5 PD.0 PA.6 PB.13 PA.7 PB.14 PA.8 PB.15 PA.9 USB_VDD33 QFN48 PA.10 PC.4 PA.11 PC.3 PA.12 PC.2 PA.13 PC.1 PA.14 PC.0 PA.15 AVDD Figure 4.3-1 QFN48 (6x6 mm) Pin Diagram Sep 9, 2019...

  • Page 32: Lqfp64 (7X7 Mm) Pin Diagram

    ISD94100 Series Technical Reference Manual 4.3.2 LQFP64 (7x7 mm) Pin Diagram PA.0 USB_VDD33 PA.1 PC.14 PA.2 PC.13 PA.3 PC.12 PA.4 PC.11 PA.5 PC.10 PA.6 PC.9 LQFP64 PA.7 PC.8 PA.8 PC.7 (7x7 mm) PA.9 PC.6 PA.10 PC.5 PA.11 PC.4 PA.12 PC.3 PA.13 PC.2 PA.14...

  • Page 33: Lqfp64 (10X10 Mm) Pin Diagram

    ISD94100 Series Technical Reference Manual 4.3.3 LQFP64 (10x10 mm) Pin Diagram PA.0 PC.15 PA.1 PC.14 PA.2 PC.13 PA.3 PC.12 PA.4 PC.11 PA.5 PC.10 PA.6 PC.9 LQFP64 PA.7 PC.8 PA.8 PC.7 (10x10 mm) PA.9 PC.6 PA.10 PC.5 PA.11 PC.4 PA.12 PC.3 PA.13 PC.2 PA.14...

  • Page 34: Pin Description

    ISD94100 Series Technical Reference Manual Pin Description MFP = Multi-function pin. Note: Pin Type I=Digital Input, O = Digital Output; A = Analog Pin; P = Power Pin; Pins Pin Name Type Description QFN48 LQFP64 LQFP64 (6x6) (7x7) (10x10) PB.0 MFP0 General purpose digital I/O pin.
  • Page 35 ISD94100 Series Technical Reference Manual Pins Pin Name Type Description QFN48 LQFP64 LQFP64 (6x6) (7x7) (10x10) DMIC_DAT0 MFP5 Digital microphone channel 0 data input pin. PB.6 MFP0 General purpose digital I/O pin. XT1_IN MFP1 External 4~24.576 MHz (high speed) crystal input pin. PWM0_CH2 MFP2 PWM0 channel2 output/capture input.
  • Page 36 ISD94100 Series Technical Reference Manual Pins Pin Name Type Description QFN48 LQFP64 LQFP64 (6x6) (7x7) (10x10) SPI1_CLK MFP3 SPI1 Serial Clock pin; or I2S1 bit clock pin. PC.3 MFP0 General purpose digital I/O pin. I2C1_SMBAL MFP1 I2C1 SMBus SMBALERT# pin TM3_EXT MFP2 Timer3 external capture input.
  • Page 37 ISD94100 Series Technical Reference Manual Pins Pin Name Type Description QFN48 LQFP64 LQFP64 (6x6) (7x7) (10x10) DPWM_LN MFP3 Audio DPWM left channel negative output pin. PC.13 MFP0 General purpose digital I/O pin. PWM0_CH3 MFP1 PWM0 channel3 output/capture input. I2C0_SCL MFP2 I2C0 clock pin. DPWM_LP MFP3 Audio DPWM left channel positive output pin.
  • Page 38 ISD94100 Series Technical Reference Manual Pins Pin Name Type Description QFN48 LQFP64 LQFP64 (6x6) (7x7) (10x10) TRACE_CLK MFP1 TPIU for ETM Tx trace clock output pin. SPI1_MOSI MFP2 SPI1 MOSI (Master Out, Slave In) pin. I2S0_MCLK MFP3 I2S0 master clock output pin. I2C1_SCL MFP4 I2C1 clock pin.
  • Page 39 ISD94100 Series Technical Reference Manual Pins Pin Name Type Description QFN48 LQFP64 LQFP64 (6x6) (7x7) (10x10) MFP2 Timer0 event counter input / toggle output. I2C1_SCL MFP3 I2C1 clock pin. I2C0_SCL MFP4 I2C0 clock pin. DPWM_SN MFP5 Audio DPWM sub-woofer channel negative output pin.
  • Page 40 ISD94100 Series Technical Reference Manual Pins Pin Name Type Description QFN48 LQFP64 LQFP64 (6x6) (7x7) (10x10) UART0_RXD MFP4 UART0 data receiver input pin. I2C1_SDA MFP5 I2C1 data input/output pin. PA.0 MFP0 General purpose digital I/O pin. SPI0_SS1 MFP1 2nd SPI0 Slave Select pin EADC0_CH0 MFP2 EADC0 channel0 analog input.
  • Page 41 ISD94100 Series Technical Reference Manual Pins Pin Name Type Description QFN48 LQFP64 LQFP64 (6x6) (7x7) (10x10) UART0_RXD MFP1 UART0 data receiver input pin.. EADC0_CH8 MFP2 EADC0 channel8 analog input. SPI2_MOSI MFP4 SPI2 MOSI (Master Out, Slave In) pin; or I2S2 data output pin.

  • Page 42: Table 4.4-1 Pin Description

    ISD94100 Series Technical Reference Manual Note: Part number ISD941XXBYI and ISD941XXBRI do not provide DPWM and DMIC functionality. Table 4.4-1 Pin Description Sep 9, 2019 Page 42 of 928 Rev1.09...

  • Page 43: Gpio Alternate Function Summary

    ISD94100 Series Technical Reference Manual GPIO Alternate Function Summary MFP* = Multi-function pin. (Reference section ) Pin function is defined in SYS_GPx_MFPx registers. For example PA0~7 pin functions are defined in SYS_GPA_MFPL register, and PA8~15 pin functions are defined in SYS_GPA_MFPH register. MFP0 MFP1 MFP2...

  • Page 44: Table 4.5-1 Gpio Alternate Function Summary

    ISD94100 Series Technical Reference Manual MFP0 MFP1 MFP2 MFP3 MFP4 MFP5 PC.2 I2C1_SMBSUS SPI1_CLK PC.3 I2C1_SMBAL TM3_EXT SPI1_SS PC.4 PWM0_CH2 CLKO SPI1_I2SMCLK PC.5 INT1 SPI2_MOSI PC.6 INT2 SPI2_MISO PC.7 SPI0_SS0 SPI2_CLK PC.8 SPI0_MOSI1 SPI2_SS PC.9 SPI0_MISO1 SPI2_I2SMCLK PC.10 SPI0_MOSI0 PWM0_BRAKE0 DPWM_RN PC.11 SPI0_MISO0...

  • Page 45: Block Diagram

    ISD94100 Series Technical Reference Manual BLOCK DIAGRAM ISD94100 Series Block Diagram Power control Timer / PWM Analog Interface Memory APROM POR / LVR / BOD Timer x4 12-bit ADC 13-ch 512KB Cortex SRAM 192KB WDT x1/WWDT x1 (DSP/FPU/ETM) CPU core LDO 200MHz 1.2V LDROM 4KB...

  • Page 46: Functional Description

    ISD94100 Series Technical Reference Manual FUNCTIONAL DESCRIPTION ® ® Cortex -M4 Core ® The Cortex -M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA AHB-Lite interfaces for best parallel performance and includes an NVIC component. The processor with optional hardware debug functionality can execute Thumb code and is compatible with other ®...
  • Page 47 ISD94100 Series Technical Reference Manual  Banked Stack Pointer (SP)  Hardware integer divide instructions, SDIV and UDIV  Handler and Thread modes  Thumb and Debug states  Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low interrupt latency ...
  • Page 48 ISD94100 Series Technical Reference Manual memory mapped devices, access to internal core registers when the core is halted, and access to debug control registers even while SYSRESETn is asserted.  Serial Wire Debug Port(SW-DP) debug access  Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches ...

  • Page 49: System Manager

    ISD94100 Series Technical Reference Manual 6.2 System Manager 6.2.1 Overview System management includes the following sections:  System Reset  System Power Distribution  SRAM Memory Organization  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System Control register 6.2.2 System Reset A system reset sets all registers to their reset values except some of the registers listed in Table...

  • Page 50: Figure 6.2-1 System Reset Sources

    ISD94100 Series Technical Reference Manual Figure 6.2-1 System Reset Sources There are a total of 9 reset sources in the ISD94100 series. In general, CPU reset is used to reset ® ® Cortex -M4 only; the other reset sources will reset Cortex -M4 and all peripherals.

  • Page 51: Figure 6.2-2 Nreset Reset Waveform

    ISD94100 Series Technical Reference Manual WDT_CTL 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 except bit 1 and bit 7 WDT_ALTCTL 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 WWDT_RLDCNT 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 WWDT_CTL 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 - 0x3F0800 WWDT_STATUS 0x0000 0x0000...

  • Page 52: Figure 6.2-3 Brown-Out Detector (Bod) Waveform

    ISD94100 Series Technical Reference Manual 6.2.2.2 Power-on Reset (POR) System power-on generates the Power-on reset (POR). When power is applied, the POR module detects the rising voltage and generates reset signal. The reset signal stays active until the voltage is ready for MCU operation. PORF bit (SYS_RSTSTS[0]) will be set to 1 to indicate a POR reset event.

  • Page 53: System Power Distribution

    ISD94100 Series Technical Reference Manual 6.2.2.5 Watchdog Timer Reset (WDT) A Watchdog reset can be identified by checking WDTRF bit (SYS_RSTSTS[2]). 6.2.2.6 CPU Lockup Reset CPU enters lockup state after CPU produces hardfault at hardfault handler. This is the result of the CPU being locked because of an unrecoverable exception, following the activation of the processor’s built in system state protection hardware.

  • Page 54: Power Modes

    ISD94100 Series Technical Reference Manual  Digital power from V and V : supplies the power to the internal regulator which provides a regulated 1.2 V power for digital operation.  USB transceiver power from USB_V offers the power for operating the USB DD33 transceiver.
  • Page 55 ISD94100 Series Technical Reference Manual Normal mode The system starts up in Normal mode. All clock sources and peripheral can be enabled or disabled by user in register CLK_PWRCTL (System Power-down Control Register), CLK_AHBCLK (AHB Devices Clock Enable Control Register), CLK_APBCLK0 (APB Devices Clock Enable Control Register 0) and CLK_APBCLK1 (APB Devices Clock Enable Control Register 1).

  • Page 56: Power Modes Settings And Wake-Up Sources

    ISD94100 Series Technical Reference Manual Deep Power-down mode (DPD) In Deep Power-down mode (DPD), all power supply is disabled except DPD control logic. The DPD control logic controls Deep Power-down mode wake-up functions. After wake-up from Deep Power- down mode (DPD), system resets and executes code from the beginning again. All peripheral configurations return to default value and all SRAM data will be lost.

  • Page 57: Figure 6.2-5 Isd94100 Series Power Mode State Machine

    ISD94100 Series Technical Reference Manual Standby Power-down mode 1 Deep Power-down mode Table 6.2.5-2 Power Mode Difference Table Note: 1. User must turn on LIRC before entering PD, LLPD and SPD0/1 mode. There are several wake-up sources in Idle mode and Power-down mode. Table 6.2.5-3 lists the available clocks for each power mode.

  • Page 58: Table 6.2.5-4 Clocks In Power Modes

    ISD94100 Series Technical Reference Manual Normal Mode Idle Mode PD, LLPD SPD0, SPD1 Halt Halt Halt HIRC Halt Halt Halt ON/OFF ON/OFF Halt LIRC ON/OFF Halt Halt Halt HCLK/PCLK Halt Halt Halt Halt Halt Halt Halt SRAM retention Halt Halt FLASH Halt Halt...
  • Page 59 ISD94100 Series Technical Reference Manual Wake-up sources in Power-down mode: Table 6.2.5-5 lists all wake-up sources that can wake chip up from power down mode to normal mode, wake-up condition and conditions on how to re-enter the power down mode again. User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter Power-down mode.

  • Page 60: Table 6.2.5-5 Re-Entering Power-Down Mode Condition

    ISD94100 Series Technical Reference Manual Threshold Wake-up (UARTx_WKSTS[2]). RS-485 AAD Mode After software writes clear RS485WKF Wake-up (UARTx_WKSTS[3]). Received FIFO After software writes clear TOUTWKF Threshold Time-out (UARTx_WKSTS[4]). Wake-up After software writes clear WKAKDONE Address match (I2C_WKSTS[1]). Then software writes 1 to clear wake-up WKIF(I2C_WKSTS[0]).

  • Page 61: Brown-Out Detector And Low Voltage Reset Controller Configuration

    ISD94100 Series Technical Reference Manual 6.2.6 Brown-out Detector and Low Voltage Reset Controller Configuration ISD94100 series is equipped with brown-out detector and low voltage reset controller function. Low voltage reset controller is enabled by setting LVREN(SYS_BODCTL[7]) to 1. Brown-out detector is enabled by setting both LVREN(SYS_BODCTL[7]) and BODEN(SYS_BODCTL[0]) to 1.

  • Page 62: System Memory Map

    ISD94100 Series Technical Reference Manual 6.2.7 System Memory Map The ISD94100 series provides 4G-byte addressing space. The memory addresses assigned to each on-chip controllers are shown in Table 6.2.7-1. The detailed register definition, memory space, and programming will be described in the following sections for each on-chip peripheral. The ISD94100 series only supports little-endian data format.

  • Page 63: Sram Memory Organization

    ISD94100 Series Technical Reference Manual System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers Table 6.2.7-1 Address Space Assignments for On-Chip Controllers 6.2.8 SRAM Memory Organization The ISD94100 series supports up to 192 KB of embedded SRAM and the SRAM organization is...

  • Page 64: Hirc Auto Trim

    ISD94100 Series Technical Reference Manual 0x3FFF_FFFF Reserved 0x2003_0000 0x2002_FFFF 160 KB SRAM 0x2000_8000 0x2000_7FFF 32 KB SRAM 0x2000_0000 Figure 6.2-7 SRAM Memory Organization SRAM address from 0x2000_0000 to 0x2000_7FFF has byte parity error check function. When CPU is accessing SRAM address from 0x2000_0000 to 0x2000_7FFF the parity error checking mechanism is operating dynamically.
  • Page 65 ISD94100 Series Technical Reference Manual Sep 9, 2019 Page 65 of 928 Rev1.09...

  • Page 66: Register Map

    ISD94100 Series Technical Reference Manual 6.2.10 Register Map R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register SYS Base Address: SYS_BA = 0x4000_0000 SYS_PDID SYS_BA+0x00 Part Device Identification Number Register 0x1DXX_05XX SYS_RSTSTS SYS_BA+0x04 R/W System Reset Status Register 0x0000_0043...

  • Page 67: Register Description

    ISD94100 Series Technical Reference Manual 6.2.11 Register Description Part Device Identification Number Register (SYS_PDID) Offset R/W Description Reset Value Register SYS_PDID SYS_BA+0x00 Part Device Identification Number Register 0x1DXX_05XX [1] Every part number has a unique default reset value. PDID PDID PDID PDID Description...
  • Page 68 ISD94100 Series Technical Reference Manual System Reset Status Register (SYS_RSTSTS) This register provides specific information for software to identify this chip’s reset source from last operation. Offset R/W Description Reset Value Register SYS_RSTSTS SYS_BA+0x04 R/W System Reset Status Register 0x0000_0043 Reserved Reserved Reserved...
  • Page 69 ISD94100 Series Technical Reference Manual Description Bits BOD Reset Flag The BOD reset flag is set by the “Reset Signal” from the Brown-Out Detector to indicate the previous reset source. BODRF 0 = No reset from BOD. 1 = The BOD had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
  • Page 70 ISD94100 Series Technical Reference Manual Peripheral Reset Control Register 0 (SYS_IPRST0) Offset R/W Description Reset Value Register SYS_IPRST0 SYS_BA+0x08 R/W Peripheral Reset Control Register 0 0x0000_0000 Reserved Reserved Reserved CRCRST Reserved PDMARST CPURST CHIPRST Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31: 8] Reserved reset value.
  • Page 71 ISD94100 Series Technical Reference Manual section 6.2.2 0 = Chip normal operation. 1 = Chip one-shot reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Sep 9, 2019 Page 71 of 928 Rev1.09...
  • Page 72 ISD94100 Series Technical Reference Manual Peripheral Reset Control Register 1 (SYS_IPRST1) Setting these bits 1 will generate asynchronous reset signals to the corresponding module controller. Users need to set these bits to 0 to release corresponding module controller from reset state. Offset R/W Description Reset Value...
  • Page 73 ISD94100 Series Technical Reference Manual 0 = SPI2 controller normal operation. 1 = SPI2 controller reset. SPI1 Controller Reset [13] SPI1RST 0 = SPI1 controller normal operation. 1 = SPI1 controller reset. SPI0 Controller Reset [12] SPI0RST 0 = SPI0 controller normal operation. 1 = SPI0 controller reset.
  • Page 74 ISD94100 Series Technical Reference Manual Peripheral Reset Control Register 2 (SYS_IPRST2) Setting these bits to 1 will generate asynchronous reset signals to the corresponding module controller. Users need to set these bits to 0 to release corresponding module controller from reset state. Offset R/W Description Reset Value...
  • Page 75 ISD94100 Series Technical Reference Manual Brown-out Detector Control Register (SYS_BODCTL) Part of the SYS_BODCTL control registers values are initialized by flash configuration and writeable bits are write-protected. Register Offset R/W Description Reset Value SYS_BODCTL SYS_BA+0x18 R/W Brown-Out Detector Control Register 0x000X_038X Reserved Reserved...
  • Page 76 ISD94100 Series Technical Reference Manual Bits Description Low Voltage Reset Enable Bit (Write Protected) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. LVREN 0 = Low Voltage Reset function Disabled. 1 = Low Voltage Reset function Enabled.
  • Page 77 ISD94100 Series Technical Reference Manual Bits Description Brown-out Detector Enable Bit (Write Protected) The default value is set by flash controller user configuration register CBODEN (CONFIG0 [19]). 0 = Brown-out Detector function Disabled. 1 = Brown-out Detector function Enabled. BODEN Note 1: The reset value of SYS_BODCTL[0] is determined by user flash configuration.
  • Page 78 ISD94100 Series Technical Reference Manual Power-on Reset Controller Register (SYS_PORCTL) Offset R/W Description Reset Value Register SYS_PORCTL SYS_BA+0x24 R/W Power-On-Reset Controller Register 0x0000_0000 Reserved Reserved POROFF POROFF Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:16] Reserved reset value.
  • Page 79 ISD94100 Series Technical Reference Manual USB PHY Control Register (SYS_USBPHY) Register Offset R/W Description Reset Value SYS_USBPHY SYS_BA+0x2C R/W USB PHY Control Register 0x0000_0000 Reserved Reserved Reserved USB_PHY_EN Reserved Bits Description Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 80 ISD94100 Series Technical Reference Manual GPIOA Low Byte Multiple Function Control Register (SYS_GPA_MFPL) Register Offset R/W Description Reset Value SYS_GPA_MFPL SYS_BA+0x30 R/W GPIOA Low Byte Multiple Function Control Register 0x0000_0000 PA7MFP PA6MFP PA5MFP PA4MFP PA3MFP PA2MFP PA1MFP PA0MFP Bits Description [31:28] PA7MFP PA.7 Multi-function Pin Selection...
  • Page 81 ISD94100 Series Technical Reference Manual GPIOA High Byte Multiple Function Control Register (SYS_GPA_MFPH) Register Offset R/W Description Reset Value SYS_GPA_MFPH SYS_BA+0x34 R/W GPIOA High Byte Multiple Function Control Register 0x0000_0000 PA15MFP PA14MFP PA13MFP PA12MFP PA11MFP PA10MFP PA9MFP PA8MFP Bits Description [31:28] PA15MFP PA.15 Multi-function Pin Selection...
  • Page 82 ISD94100 Series Technical Reference Manual GPIOB Low Byte Multiple Function Control Register (SYS_GPB_MFPL) Register Offset R/W Description Reset Value SYS_GPB_MFPL SYS_BA+0x38 R/W GPIOB Low Byte Multiple Function Control Register 0x0110_0000 PB7MFP PB6MFP PB5MFP PB4MFP PB3MFP PB2MFP PB1MFP PB0MFP Bits Description [31:28] PB7MFP PB.7 Multi-function Pin Selection...
  • Page 83 ISD94100 Series Technical Reference Manual GPIOB High Byte Multiple Function Control Register (SYS_GPB_MFPH) Register Offset R/W Description Reset Value SYS_GPB_MFPH SYS_BA+0x3C R/W GPIOB High Byte Multiple Function Control Register 0x0000_0000 PB15MFP PB14MFP PB13MFP Reserved Reserved PB9MFP PB8MFP Bits Description [31:28] PB15MFP PB.15 Multi-function Pin Selection [27:24]...
  • Page 84 ISD94100 Series Technical Reference Manual GPIOC Low Byte Multiple Function Control Register (SYS_GPC_MFPL) Register Offset R/W Description Reset Value SYS_GPC_MFPL SYS_BA+0x40 R/W GPIOC Low Byte Multiple Function Control Register 0x0000_0000 PC7MFP PC6MFP PC5MFP PC4MFP PC3MFP PC2MFP PC1MFP PC0MFP Bits Description [31:28] PC7MFP PC.7 Multi-function Pin Selection...
  • Page 85 ISD94100 Series Technical Reference Manual GPIOC High Byte Multiple Function Control Register (SYS_GPC_MFPH) Register Offset R/W Description Reset Value SYS_GPC_MFPH SYS_BA+0x44 R/W GPIOC High Byte Multiple Function Control Register 0x0000_0000 PC15MFP PC14MFP PC13MFP PC12MFP PC11MFP PC10MFP PC9MFP PC8MFP Bits Description [31:28] PC15MFP PC.15 Multi-function Pin Selection...
  • Page 86 ISD94100 Series Technical Reference Manual GPIOD Low Byte Multiple Function Control Register (SYS_GPD_MFPL) Register Offset R/W Description Reset Value SYS_GPD_MFPL SYS_BA+0x48 R/W GPIOD Low Byte Multiple Function Control Register 0x0000_0000 PD7MFP PD6MFP PD5MFP PD4MFP PD3MFP PD2MFP PD1MFP PD0MFP Bits Description [31:28] PD7MFP PD.7 Multi-function Pin Selection...
  • Page 87 ISD94100 Series Technical Reference Manual GPIOD High Byte Multiple Function Control Register (SYS_GPD_MFPH) Register Offset R/W Description Reset Value SYS_GPD_MFPH SYS_BA+0x4C R/W GPIOD High Byte Multiple Function Control Register 0x0000_0011 PD15MFP PD14MFP PD13MFP PD12MFP PD11MFP PD10MFP PD9MFP PD8MFP Bits Description [31:28] PD15MFP PD.15 Multi-function Pin Selection...
  • Page 88 ISD94100 Series Technical Reference Manual System SRAM Parity Error Interrupt Enable Control Register (SYS_SRAM_INTCTL) Offset R/W Description Reset Value Register SYS_SRAM_INTCTL SYS_BA+0xC0 R/W System SRAM Interrupt Enable Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PERRIEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:1] Reserved reset value.
  • Page 89 ISD94100 Series Technical Reference Manual System SRAM Parity Check Status Register (SYS_SRAM_STATUS) Offset R/W Description Reset Value Register SYS_SRAM_STATUS SYS_BA+0xC4 R/W System SRAM Parity Error Status Register 0x0000_0000 Reserved Reserved Reserved Reserved PERRIF Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:1] Reserved reset value.
  • Page 90 ISD94100 Series Technical Reference Manual System SRAM Parity Error Address Register (SYS_SRAM_ERRADDR) Offset R/W Description Reset Value Register SYS_SRAM_ERRADDR SYS_BA+0xC8 System SRAM Parity Check Error Address Register 0x0000_0000 ERRADDR ERRADDR ERRADDR ERRADDR Description Bits System SRAM Parity Error Address [31:0] ERRADDR This register shows system SRAM parity error byte address.
  • Page 91 ISD94100 Series Technical Reference Manual HIRC Trim Control Register (SYS_IRCTCTL) Register Offset R/W Description Reset Value SYS_IRCTCTL SYS_BA+0xF0 R/W HIRC Trim Control Register 0x0000_0000 Reserved Reserved Reserved REFCKSEL Reserved CESTOPEN RETRYCNT LOOPSEL Reserved FREQSEL Bits Description Reserved. Any values read should be ignored. When writing to this field always write with Reserved [31:11] reset value.
  • Page 92 ISD94100 Series Technical Reference Manual on the average frequency difference in 4 clocks of reference clock. Reserved. Any values read should be ignored. When writing to this field always write with [3:2] Reserved reset value. Trim Frequency Selection This field indicates the target frequency of 48 MHz and 49.152 MHz internal high speed RC oscillator (HIRC) auto trim.
  • Page 93 ISD94100 Series Technical Reference Manual HIRC Trim Interrupt Enable Register (SYS_IRCTIEN) Register Offset R/W Description Reset Value SYS_IRCTIEN SYS_BA+0xF4 R/W HIRC Trim Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKEIEN TFAILIEN Reserved Bits Description Reserved. Any values read should be ignored. When writing to this field always write with Reserved [31:3] reset value.
  • Page 94 ISD94100 Series Technical Reference Manual HIRC Trim Interrupt Status Register (SYS_IRCTISTS) Register Offset R/W Description Reset Value SYS_IRCTISTS SYS_BA+0xF8 R/W HIRC Trim Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKERRIF TFAILIF FREQLOCK Bits Description Reserved. Any values read should be ignored. When writing to this field always write with Reserved [31:3] reset value.
  • Page 95 ISD94100 Series Technical Reference Manual Register Lock Control Register (SYS_REGLCTL) This register is written to disable/enable register protection and read for the REGLCTL status. Some of the system control registers are protected to avoid inadvertent write that may disturb the chip operation.
  • Page 96 ISD94100 Series Technical Reference Manual CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable) CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select) CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select) CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select) CLK_CLKDSTS: address 0x4000_0274 NMIEN: address 0x4000_0300 FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register)
  • Page 97 ISD94100 Series Technical Reference Manual HIRC Trim Value Register (SYS_RCADJ) Register Offset R/W Description Reset Value SYS_BA+0x110 R/W HIRC Trim Value Register 0x0000_0XXX SYS_RCADJ Reserved Reserved Reserved RCADJ RCADJ Bits Description Reserved. Any values read should be ignored. When writing to this field always write with Reserved [31:10] reset value.

  • Page 98: System Timer (Systick)

    ISD94100 Series Technical Reference Manual 6.2.12 System Timer (SysTick) The Cortex ® -M4 integrates a system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks.
  • Page 99 ISD94100 Series Technical Reference Manual 6.2.12.2 System Timer Control Register Description SysTick Control and Status Register (SYST_CTRL) Offset R/W Description Reset Value Register SYST_CTRL SCS_BA+0x10 R/W SysTick Control and Status Register 0x0000_0000 Reserved Reserved COUNTFLAG Reserved Reserved CLKSRC TICKINT ENABLE Description Bits Reserved.
  • Page 100 ISD94100 Series Technical Reference Manual SysTick Reload Value Register (SYST_LOAD) Offset R/W Description Reset Value Register SYST_LOAD SCS_BA+0x14 R/W SysTick Reload Value Register 0x0000_0000 Reserved RELOAD RELOAD RELOAD Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:24] Reserved reset value.
  • Page 101 ISD94100 Series Technical Reference Manual SysTick Current Value Register (SYST_VAL) Offset R/W Description Reset Value Register SYST_VAL SCS_BA+0x18 R/W SysTick Current Value Register 0x0000_0000 Reserved CURRENT CURRENT CURRENT Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:24] Reserved reset value.

  • Page 102: Nested Vectored Interrupt Controller (Nvic)

    ISD94100 Series Technical Reference Manual 6.2.13 Nested Vectored Interrupt Controller (NVIC) The NVIC and the processor core interface are closely coupled to enable low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC from privileged mode, but you can cause interrupts to enter a pending state in user mode if you enable the Configuration and Control Register.

  • Page 103: Table 6.2.13-1 Exception Model

    ISD94100 Series Technical Reference Manual Debug Monitor 0x00000030 Configurable Reserved Reserved PendSV 0x00000038 Configurable SysTick 0x0000003C Configurable 0x00000000 + Interrupt (IRQ0 ~ IRQ) 16 ~ 111 Configurable (Vector Number)*4 Table 6.2.13-1 Exception Model Interrupt Number Vector Interrupt Name Interrupt Description (Bit Interrupt Number...

  • Page 104: Table 6.2.13-2 Interrupt Number Table

    ISD94100 Series Technical Reference Manual BRAKE0_INT PWM0 brake interrupt PWM0_P0_INT PWM0 pair 0 interrupt PWM0_P1_INT PWM0 pair 1 interrupt PWM0_P2_INT PWM0 pair 2 interrupt 44 ~ 47 28 ~ 31 Reserved Reserved TMR0_INT Timer 0 interrupt TMR1_INT Timer 1 interrupt TMR2_INT Timer 2 interrupt TMR3_INT...
  • Page 105 ISD94100 Series Technical Reference Manual 6.2.13.2 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not activate.
  • Page 106 ISD94100 Series Technical Reference Manual 6.2.13.3 NVIC Control Registers R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register NVIC Base Address: NVIC_BA = 0xE000_E100 NVIC_ISER0 0xE000E100 R/W IRQ0 ~ IRQ31 Set-Enable Control Register 0x0000_0000 NVIC_ISER1 0xE000E104...
  • Page 107 ISD94100 Series Technical Reference Manual IRQ0 ~ IRQ31 Set-Enable Control Register (NVIC_ISER0) Offset R/W Description Reset Value Register NVIC_ISER0 0xE000E100 R/W IRQ0 ~ IRQ31 Set-Enable Control Register 0x0000_0000 SETENA SETENA SETENA SETENA Description Bits Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER2 registers enable interrupts, and show which interrupts are enabled.
  • Page 108 ISD94100 Series Technical Reference Manual IRQ32 ~ IRQ63 Set-Enable Control Register (NVIC_ISER1) Offset R/W Description Reset Value Register NVIC_ISER1 0xE000E104 R/W IRQ32 ~ IRQ63 Set-Enable Control Register 0x0000_0000 SETENA SETENA SETENA SETENA Description Bits Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER2 registers enable interrupts, and show which interrupts are enabled Write Operation: 0 = No effect.
  • Page 109 ISD94100 Series Technical Reference Manual IRQ64 ~ IRQ95 Set-Enable Control Register (NVIC_ISER2) Register Offset R/W Description Reset Value NVIC_ISER2 0xE000E108 R/W IRQ64 ~ IRQ95 Set-Enable Control Register 0x0000_0000 SETENA SETENA SETENA SETENA Bits Description Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER2 registers enable interrupts, and show which interrupts are enabled Write Operation: 0 = No effect.
  • Page 110 ISD94100 Series Technical Reference Manual IRQ0 ~ IRQ31 Clear-Enable Control Register (NVIC_ICER0) Offset R/W Description Reset Value Register NVIC_ICER0 0xE000E180 R/W IRQ0 ~ IRQ31 Clear-Enable Control Register 0x0000_0000 CALENA CALENA CALENA CALENA Description Bits Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER2 registers disable interrupts, and show which interrupts are enabled.
  • Page 111 ISD94100 Series Technical Reference Manual IRQ32 ~ IRQ63 Clear-Enable Control Register (NVIC_ICER1) Offset R/W Description Reset Value Register NVIC_ICER1 0xE000E184 R/W IRQ32 ~ IRQ63 Clear-Enable Control Register 0x0000_0000 CALENA CALENA CALENA CALENA Description Bits Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER2 registers disable interrupts, and show which interrupts are enabled.
  • Page 112 ISD94100 Series Technical Reference Manual IRQ64 ~ IRQ95 Clear-Enable Control Register (NVIC_ICER2) Register Offset R/W Description Reset Value NVIC_ICER2 0xE000E188 R/W IRQ64 ~ IRQ95 Clear-Enable Control Register 0x0000_0000 CALENA CALENA CALENA CALENA Bits Description Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER2 registers disable interrupts, and show which interrupts are enabled.
  • Page 113 ISD94100 Series Technical Reference Manual IRQ0 ~ IRQ31 Set-Pending Control Register (NVIC_ISPR0) Offset R/W Description Reset Value Register NVIC_ISPR0 0xE000E200 R/W IRQ0 ~ IRQ31 Set-Pending Control Register 0x0000_0000 SETPEND SETPEND SETPEND SETPEND Description Bits Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR2 registers force interrupts into the pending state, and show which interrupts are pending Write Operation: 0 = No effect.
  • Page 114 ISD94100 Series Technical Reference Manual IRQ32 ~ IRQ63 Set-Pending Control Register (NVIC_ISPR1) Offset R/W Description Reset Value Register NVIC_ISPR1 0xE000E204 R/W IRQ32 ~ IRQ63 Set-Pending Control Register 0x0000_0000 SETPEND SETPEND SETPEND SETPEND Description Bits Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR2 registers force interrupts into the pending state, and show which interrupts are pending Write Operation: 0 = No effect.
  • Page 115 ISD94100 Series Technical Reference Manual IRQ64 ~ IRQ95 Set-Pending Control Register (NVIC_ISPR2) Offset R/W Description Reset Value Register NVIC_ISPR2 0xE000E208 R/W IRQ64 ~ IRQ95 Set-Pending Control Register 0x0000_0000 SETPEND SETPEND SETPEND SETPEND Description Bits Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR2 registers force interrupts into the pending state, and show which interrupts are pending Write Operation: 0 = No effect.
  • Page 116 ISD94100 Series Technical Reference Manual IRQ0 ~ IRQ31 Clear-Pending Control Register (NVIC_ICPR0) Offset R/W Description Reset Value Register NVIC_ICPR0 0xE000E280 R/W IRQ0 ~ IRQ31 Clear-Pending Control Register 0x0000_0000 CALPEND CALPEND CALPEND CALPEND Description Bits Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending Write Operation: 0 = No effect.
  • Page 117 ISD94100 Series Technical Reference Manual IRQ32 ~ IRQ63 Clear-Pending Control Register (NVIC_ICPR1) Offset R/W Description Reset Value Register NVIC_ICPR1 0xE000E284 R/W IRQ32 ~ IRQ63 Clear-Pending Control Register 0x0000_0000 CALPEND CALPEND CALPEND CALPEND Description Bits Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending Write Operation: 0 = No effect.
  • Page 118 ISD94100 Series Technical Reference Manual IRQ64 ~ IRQ95 Clear-Pending Control Register (NVIC_ICPR2) Register Offset R/W Description Reset Value NVIC_ICPR2 0xE000E288 R/W IRQ64 ~ IRQ95 Clear-Pending Control Register 0x0000_0000 CALPEND CALPEND CALPEND CALPEND Bits Description Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending Write Operation: 0 = No effect.
  • Page 119 ISD94100 Series Technical Reference Manual IRQ0 ~ IRQ31 Active Bit Register (NVIC_IABR0) Offset R/W Description Reset Value Register NVIC_IABR0 0xE000E300 R/W IRQ0 ~ IRQ31 Active Bit Register 0x0000_0000 ACTIVE ACTIVE ACTIVE ACTIVE Description Bits Interrupt Active Flags The NVIC_IABR0-NVIC_IABR2 registers indicate which interrupts are active. [31:0] ACTIVE 0 = interrupt not active.
  • Page 120 ISD94100 Series Technical Reference Manual IRQ32 ~ IRQ63 Active Bit Register (NVIC_IABR1) Offset R/W Description Reset Value Register NVIC_IABR1 0xE000E304 R/W IRQ32 ~ IRQ63 Active Bit Register 0x0000_0000 ACTIVE ACTIVE ACTIVE ACTIVE Description Bits Interrupt Active Flags The NVIC_IABR0-NVIC_IABR2 registers indicate which interrupts are active. [31:0] ACTIVE 0 = interrupt not active.
  • Page 121 ISD94100 Series Technical Reference Manual IRQ64 ~ IRQ95 Active Bit Register (NVIC_IABR2) Register Offset R/W Description Reset Value NVIC_IABR2 0xE000E308 R/W IRQ64 ~ IRQ95 Active Bit Register 0x0000_0000 ACTIVE ACTIVE ACTIVE ACTIVE Bits Description Interrupt Active Flags The NVIC_IABR0-NVIC_IABR2 registers indicate which interrupts are active. ACTIVE [31:0] 0 = interrupt not active.
  • Page 122 ISD94100 Series Technical Reference Manual IRQ0 ~ IRQ95 Interrupt Priority Register (NVIC_IPRn) Offset R/W Description Reset Value Register NVIC_IPRn 0xE000E400 R/W IRQ0 ~ IRQ95 Priority Control Register 0x0000_0000 +0x4*n n=0,1..23 PRI_4n_3 Reserved PRI_4n_2 Reserved PRI_4n_1 Reserved PRI_4n_0 Reserved Description Bits Priority of IRQ_4n+3 [31:28] PRI_4n_3...
  • Page 123 ISD94100 Series Technical Reference Manual Software Trigger Interrupt Register (STIR) Offset R/W Description Reset Value Register STIR 0xE000F000 Software Trigger Interrupt Registers 0x0000_0000 Reserved Reserved Reserved INTID INTID Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 124 ISD94100 Series Technical Reference Manual 6.2.13.4 NMI Control Registers R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register NMI Base Address: NMI_BA = 0x4000_0300 NMIEN NMI_BA+0x00 R/W NMI Source Interrupt Enable Register 0x0000_0000 NMISTS NMI_BA+0x04...
  • Page 125 ISD94100 Series Technical Reference Manual NMI Source Interrupt Enable Register (NMIEN) Offset R/W Description Reset Value Register NMIEN NMI_BA+0x00 R/W NMI Source Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved UART0_INT EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 Reserved RTC_INT Reserved CLKFAIL SRAM_PERR PWRWU_INT IRC_INT BODOUT...
  • Page 126 ISD94100 Series Technical Reference Manual External Interrupt 0 NMI Source Enable (Write Protected) 0 = External interrupt 0 NMI source Disabled. EINT0 1 = External interrupt 0 NMI source Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Reserved.
  • Page 127 ISD94100 Series Technical Reference Manual NMI Source Interrupt Status Register (NMISTS) Offset R/W Description Reset Value Register NMISTS NMI_BA+0x04 NMI source interrupt Status Register 0x0000_0000 Reserved Reserved Reserved UART0_INT EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 Reserved RTC_INT Reserved CLKFAIL SRAM_PERR PWRWU_INT IRC_INT BODOUT Description...
  • Page 128 ISD94100 Series Technical Reference Manual RTC Interrupt Flag (Read Only) RTC_INT 0 = RTC interrupt is deasserted. 1 = RTC interrupt is asserted. Reserved. Any values read should be ignored. When writing to this field always write with Reserved reset value. Clock Fail Detected Interrupt Flag (Read Only) CLKFAIL 0 = Clock fail detected interrupt is deasserted.
  • Page 129 ISD94100 Series Technical Reference Manual 6.2.13.5 AHB Bus Matrix Priority Control Register R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register AHB Base Address: AHB_BA = 0x4000_0400 AHBMCTL 0x40000400 R/W AHB Bus Matrix Priority Control Register 0x0000_0001 Sep 9, 2019 Page 129 of 928...
  • Page 130 ISD94100 Series Technical Reference Manual AHB Bus Matrix Priority Control Register (AHBMCTL) Offset R/W Description Reset Value Register AHBMCTL 0x40000400 R/W AHB Bus Matrix Priority Control Register 0x0000_0001 Reserved Reserved Reserved Reserved INTACTEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:1] Reserved reset value.

  • Page 131: System Control Register

    ISD94100 Series Technical Reference Manual 6.2.14 System Control Register The Cortex ® -M4 status and operation mode control are managed by System Control Registers. These registers also manage CPUID, Cortex ® -M4 interrupt priority and Cortex ® -M4 power management. ®...
  • Page 132 ISD94100 Series Technical Reference Manual Interrupt Control State Register (ICSR) Offset R/W Description Reset Value Register ICSR SCS_BA+0xD04 R/W Interrupt Control and State Register 0x0000_0000 PENDSVRTC_ PENDSTRTC_ NMIPENDSET Reserved PENDSVSET PENDSTSET Reserved ISRPREEMPT ISRPENDING Reserved VECTPENDING VECTPENDING RETTOBASE Reserved Reserved VECTACTIVE Description Bits...
  • Page 133 ISD94100 Series Technical Reference Manual SysTick Exception Set-pending Bit Write Operation: 0 = No effect. PENDSTSET [26] 1 = Changes SysTick exception state to pending. Read Operation: 0 = SysTick exception is not pending. 1 = SysTick exception is pending. SysTick Exception Clear-pending Bit Write Operation: PENDSTRTC_CA...
  • Page 134 ISD94100 Series Technical Reference Manual Application Interrupt and Reset Control Register (AIRCR) Offset R/W Description Reset Value Register AIRCR SCS_BA+0xD0C R/W Application Interrupt and Reset Control Register 0xFA05_0000 VECTORKEY VECTORKEY ENDIANNESS Reserved PRIGROUP SYSRESETRE VECTCLRAC Reserved VECTRESET TIVE Description Bits Register Access Key When writing this register, this field should be 0x05FA, otherwise the write action will be [31:16]...

  • Page 135: Table 6.2.14-1 Priority Grouping

    ISD94100 Series Technical Reference Manual Group Number Group Binary Point Subpriority Bits Subpriorities PRIGROUP Priorities Priority Bits 0b000 bxxxxxxx.y [7:1] 0b001 bxxxxxx.yy [7:2] [1:0] 0b010 bxxxxx.yyy [7:3] [2:0] 0b011 bxxxx.yyyy [7:4] [3;0] 0b100 bxxx.yyyyy [7:5] [4:0] 0b101 bxx.yyyyyy [7:6] [5:0] 0b110 bx.yyyyyyy [6:0]...
  • Page 136 ISD94100 Series Technical Reference Manual System Control Register (SCR) Offset R/W Description Reset Value Register SCS_BA+0xD10 R/W System Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SEVONPEND Reserved SLEEPDEEP SLEEPONEXIT Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:5] Reserved reset value.
  • Page 137 ISD94100 Series Technical Reference Manual System Handler Priority Register 1 (SHPR1) Offset R/W Description Reset Value Register SHPR1 SCS_BA+0xD18 R/W System Handler Priority Register 1 0x0000_0000 Reserved PRI_6 Reserved PRI_5 Reserved PRI_4 Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:24] Reserved reset value.
  • Page 138 ISD94100 Series Technical Reference Manual System Handler Priority Register 2 (SHPR2) Offset R/W Description Reset Value Register SHPR2 SCS_BA+0xD1C R/W System Handler Priority Register 2 0x0000_0000 PRI_11 Reserved Reserved Reserved Reserved Description Bits Priority of System Handler 11 – SVCall [31:28] PRI_11 “0”...
  • Page 139 ISD94100 Series Technical Reference Manual System Handler Priority Register 3 (SHPR3) Offset R/W Description Reset Value Register SHPR3 SCS_BA+0xD20 R/W System Handler Priority Register 3 0x0000_0000 PRI_15 Reserved PRI_14 Reserved Reserved Reserved Description Bits Priority of System Handler 15 – SysTick [31:28] PRI_15 “0”...

  • Page 140: Clock Controller

    ISD94100 Series Technical Reference Manual 6.3 Clock Controller 6.3.1 Overview The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down ®...

  • Page 141: Figure 6.3-1 Clock Generator Global View Diagram

    ISD94100 Series Technical Reference Manual HIRC LIRC PWM0 EADC 48 / 49.152 4~24.576 32.768 I2C0 I2C1 SPI0 PCLK0 PCLK1 HIRC PDMA /1,/2,/4,/8,/16 SPI2 SPI1 PLLFOUT TMR2 PLL FOUT SRAM TMR0 TMR1 TMR3 CLK_PLLCTL[19] DMIC DPWM HIRC LIRC PLLFOUT HCLK 1/(HCLKDIV+1) /1,/2,/4,/8,/16 PCLK1 1/(EADCDIV+1)

  • Page 142: Clock Generator

    ISD94100 Series Technical Reference Manual 6.3.2 Clock Generator Five clock sources can be used to drive all the internal clocks:  32.768 kHz external low speed crystal oscillator (LXT)  4~24.576 MHz external high speed crystal oscillator (HXT)  Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected from external 4~24.576 MHz external high speed crystal (HXT) or internal high speed oscillator (HIRC) ...

  • Page 143: System Clock And Systick Clock

    ISD94100 Series Technical Reference Manual 6.3.3 System Clock and SysTick Clock Five clock sources can be used to drive the system clock (HCLK), as shown in Figure 6.3-3. Clock source can be chosen by configuring HCLKSEL bits(CLK_CLKSEL0[2:0]). HCLKSEL (CLK_CLKSEL0[2:0]) HIRC CPUCLK LIRC HCLK...

  • Page 144: Figure 6.3-4 Hxt Stop Protect Procedure

    ISD94100 Series Technical Reference Manual Set HXTFDEN To enable HXT clock detector HXTFIF = 1? System clock source = System clock keep “ HXT” or “ PLL with original clock HXT” ? Switch system clock to HIRC Figure 6.3-4 HXT Stop Protect Procedure The SysTick clock source can be from CPU clock or external reference clock, determined by CLKSRC bit (SYST_CTRL[2]).

  • Page 145: Peripheral Clock

    ISD94100 Series Technical Reference Manual 6.3.4 Peripheral Clock Each peripheral module can have its own clock source selection and configuration, please refer to CLK_CLKSEL1 and CLK_CLKSEL2 register description for more detailed information. 6.3.5 Power-down Mode Clock Different power down modes have different impact on the system clocks. Under a certain power down mode, some clock sources (including system clocks and peripheral clocks) are disabled while some other clock sources are still available.

  • Page 146: Clock Setting Limitation

    ISD94100 Series Technical Reference Manual 6.3.7 Clock Setting Limitation The maximum frequency of PCLK0 and PCLK1 is 90 MHz. If the frequency of HCLK greater than 90 MHz, the APB1DIV (CLK_PCLKDIV[6:4]) and APB0DIV(CLK_PCLKDIV[2:0]) must be set to the appropriate value to keep the PCLK0 and PCLK1 less than or equal to 90MHz. Sep 9, 2019 Page 146 of 928 Rev1.09...

  • Page 147: Register Map

    ISD94100 Series Technical Reference Manual 6.3.8 Register Map R: read only, W: write only, R/W: both read and write Offset Description Reset Value Register CLK Base Address: CLK_BA = 0x4000_0200 CLK_PWRCTL CLK_BA+0x00 System Power-down Control Register 0x0000_1C1X CLK_AHBCLK CLK_BA+0x04 AHB Devices Clock Enable Control Register 0x0000_8004 CLK_APBCLK0 CLK_BA+0x08...
  • Page 148 ISD94100 Series Technical Reference Manual CLK_IOPDCTL CLK_BA+0xB0 GPIO Standby Power-down Control Register 0x0000_0000 Note: Any register not listed here is reserved and must not be written. The result of a read operation on these bits is undefined. The reserved register fields that listed in register description must be written to their reset value. Writing reserved fields with other than reset values may produce undefined results.

  • Page 149: Register Description

    ISD94100 Series Technical Reference Manual 6.3.9 Register Description System Power-down Control Register (CLK_PWRCTL) Offset R/W Description Reset Value Register CLK_PWRCTL CLK_BA+0x00 R/W System Power-down Control Register 0x0000_1C1X Reserved Reserved Reserved HXTTBEN HXTSELTYP HXTGAIN PDWTCPU Reserved PDEN PDWKIF PDWKIEN PDWKDLY LIRCEN HIRCEN LXTEN HXTEN...
  • Page 150 ISD94100 Series Technical Reference Manual 1 = Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU runs WFI instruction. Note: This bit is write protected. Refer to the SYS_REGLCTL register. System Power-down Enable (Write Protected) When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
  • Page 151 ISD94100 Series Technical Reference Manual LXT Enable Bit (Write Protected) 0 = External low speed crystal (LXT) Disabled. LXTEN 1 = External low speed crystal (LXT) Enabled. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: The reset value of this bit is 0. HXT Enable Bit (Write Protected) The bit default value is set by flash controller user configuration register CONFIG0 [26].
  • Page 152 ISD94100 Series Technical Reference Manual AHB Devices Clock Enable Control Register (CLK_AHBCLK) The bits in this register are used to enable/disable clock for system clock, AHB bus devices clock. Offset R/W Description Reset Value Register CLK_AHBCLK CLK_BA+0x04 R/W AHB Devices Clock Enable Control Register 0x0000_8004 Reserved Reserved...
  • Page 153 ISD94100 Series Technical Reference Manual APB Devices Clock Enable Control Register (CLK_APBCLK0) The bits in this register are used to enable/disable clock for peripheral controller clocks. Offset R/W Description Reset Value Register CLK_APBCLK0 CLK_BA+0x08 R/W APB Devices Clock Enable Control Register 0 0x0000_0001 Reserved I2S0CKEN...
  • Page 154 ISD94100 Series Technical Reference Manual 1 = SPI1 clock Enabled. SPI0 Clock Enable Bit [12] SPI0CKEN 0 = SPI0 clock Disabled. 1 = SPI0 clock Enabled. Reserved. Any values read should be ignored. When writing to this field always write with Reserved [11:10] reset value.
  • Page 155 ISD94100 Series Technical Reference Manual APB Devices Clock Enable Control Register 1 (CLK_APBCLK1) The bits in this register are used to enable/disable clock for peripheral controller clocks. Offset R/W Description Reset Value Register CLK_APBCLK1 CLK_BA+0x0C R/W APB Devices Clock Enable Control Register 1 0x0000_0000 Reserved Reserved...
  • Page 156 ISD94100 Series Technical Reference Manual Clock Source Select Control Register 0 (CLK_CLKSEL0) Offset R/W Description Reset Value Register CLK_CLKSEL0 CLK_BA+0x10 R/W Clock Source Select Control Register 0 0x0000_003X Reserved HIRCFSEL Reserved Reserved Reserved STCLKSEL HCLKSEL Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:25] Reserved reset value.
  • Page 157 ISD94100 Series Technical Reference Manual 001 = Clock source from LXT. 010 = Clock source from PLL. 011 = Clock source from LIRC. 111= Clock source from HIRC. Other = Reserved. Do not use. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Sep 9, 2019 Page 157 of 928 Rev1.09...
  • Page 158 ISD94100 Series Technical Reference Manual Clock Source Select Control Register 1 (CLK_CLKSEL1) Before clock switching, the related clock sources (pre-selected and newly-selected) must be turned on. Offset R/W Description Reset Value Register CLK_CLKSEL1 CLK_BA+0x14 R/W Clock Source Select Control Register 1 0xB377_7703 WWDTSEL CLKOSEL...
  • Page 159 ISD94100 Series Technical Reference Manual 101 = Clock source from internal low speed RC oscillator (LIRC). 111 = Clock source from internal high speed RC oscillator (HIRC). Others = Reserved. Do not use. Reserved. Any values read should be ignored. When writing to this field always write with [19] Reserved reset value.
  • Page 160 ISD94100 Series Technical Reference Manual Clock Source Select Control Register 2 (CLK_CLKSEL2) Before clock switching, the related clock sources (pre-select and new-select) must be turned on. Offset R/W Description Reset Value Register CLK_CLKSEL2 CLK_BA+0x18 R/W Clock Source Select Control Register 2 0x0000_00A9 Reserved Reserved...
  • Page 161 ISD94100 Series Technical Reference Manual 11 = Clock source from internal high speed RC oscillator (HIRC). SPI0 Clock Source Selection 00 = Clock source from external high speed crystal oscillator (HXT). [3:2] SPI0SEL 01 = Clock source from PLL. 10 = Clock source from PCLK0. 11 = Clock source from internal high speed RC oscillator (HIRC).
  • Page 162 ISD94100 Series Technical Reference Manual Clock Source Select Control Register 3 (CLK_CLKSEL3) Before clock switching, the related clock sources (pre-select and new-select) must be turned on. Offset R/W Description Reset Value Register CLK_CLKSEL3 CLK_BA+0x1C R/W Clock Source Select Control Register 3 0x0000_0000 Reserved Reserved...
  • Page 163 ISD94100 Series Technical Reference Manual Clock Divider Number Register 0 (CLK_CLKDIV0) Offset R/W Description Reset Value Register CLK_CLKDIV0 CLK_BA+0x20 R/W Clock Divider Number Register 0 0x0006_0000 Reserved EADCDIV Reserved UART0DIV USBDIV HCLKDIV Description Bits Reserved. Any values read should be ignored. When writing to this field always write with Reserved [31:24] reset value.
  • Page 164 ISD94100 Series Technical Reference Manual Clock Source Select Control Register 4 (CLK_CLKSEL4) Offset R/W Description Reset Value Register CLK_CLKSEL4 CLK_BA+0x24 R/W Clock Source Select Control Register 4 0x0000_0000 Reserved USBSEL Reserved Reserved Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with Reserved [31:25] reset value.
  • Page 165 ISD94100 Series Technical Reference Manual APB Clock Divider Register (CLK_PCLKDIV) Offset R/W Description Reset Value Register CLK_PCLKDIV CLK_BA+0x34 R/W APB Clock Divider Register 0x0000_0000 Reserved Reserved Reserved Reserved APB1DIV Reserved APB0DIV Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:7] Reserved reset value.
  • Page 166 ISD94100 Series Technical Reference Manual PLL Control Register (CLK_PLLCTL) Offset R/W Description Reset Value Register CLK_PLLCTL CLK_BA+0x40 R/W PLL Control Register 0x0005_8430 Reserved Reserved PLLSRC STBSEL OUTDIV INDIV FBDIV FBDIV Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:24] Reserved reset value.

  • Page 167: Table 6.3.9-1 The Symbol Definition Of Pll Output Frequency Formula

    ISD94100 Series Technical Reference Manual 0 = PLL is in normal mode. 1 = PLL is in Power-down mode (default). Note: This bit is write protected. Refer to the SYS_REGLCTL register. PLL Output Divider Control (Write Protected) [15:14] OUTDIV Refer to the formulas below the table. Note: This bit is write protected.
  • Page 168 ISD94100 Series Technical Reference Manual Clock Status Monitor Register (CLK_STATUS) The bits in this register are used to monitor if the chip clock source is stable or not, and whether the clock switch is failed. Offset R/W Description Reset Value Register CLK_STATUS CLK_BA+0x50...
  • Page 169 ISD94100 Series Technical Reference Manual 0 = External high speed crystal oscillator (HXT) clock is not stable or disabled. 1 = External high speed crystal oscillator (HXT) clock is stable and enabled. Sep 9, 2019 Page 169 of 928 Rev1.09...
  • Page 170 ISD94100 Series Technical Reference Manual Clock Output Control Register (CLK_CLKOCTL) Offset R/W Description Reset Value Register CLK_CLKOCTL CLK_BA+0x60 R/W Clock Output Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CLK1HZEN DIV1EN CLKOEN FREQSEL Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:7] Reserved reset value.
  • Page 171 ISD94100 Series Technical Reference Manual Clock Fail Detector Control Register (CLK_CLKDCTL) Offset R/W Description Reset Value Register CLK_CLKDCTL CLK_BA+0x70 R/W Clock Fail Detector Control Register 0x0000_0000 Reserved Reserved HXTFQIEN HXTFQDEN Reserved LXTFIEN LXTFDEN Reserved Reserved HXTFIEN HXTFDEN Reserved Description Bits Reserved.
  • Page 172 ISD94100 Series Technical Reference Manual 0 = External high speed crystal oscillator (HXT) clock fail detector Disabled. 1 = External high speed crystal oscillator (HXT) clock fail detector Enabled. Reserved. Any values read should be ignored. When writing to this field always write with [3:0] Reserved reset value.
  • Page 173 ISD94100 Series Technical Reference Manual Clock Fail Detector Status Register (CLK_CLKDSTS) Offset R/W Description Reset Value Register CLK_CLKDSTS CLK_BA+0x74 R/W Clock Fail Detector Status Register 0x0000_0000 Reserved Reserved Reserved HXTFQIF Reserved LXTFIF HXTFIF Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 174 ISD94100 Series Technical Reference Manual Clock Frequency Detector Upper Boundary Register (CLK_CDUPB) Offset R/W Description Reset Value Register Clock Frequency Range Detector Upper Boundary CLK_CDUPB CLK_BA+0x78 0x0000_0000 Register Reserved Reserved Reserved UPERBD UPERBD Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:10] Reserved reset value.
  • Page 175 ISD94100 Series Technical Reference Manual Clock Frequency Detector Lower Boundary Register (CLK_CDLOWB) Offset R/W Description Reset Value Register Clock Frequency Range Detector Lower Boundary CLK_CDLOWB CLK_BA+0x7C 0x0000_0000 Register Reserved Reserved Reserved LOWERBD LOWERBD Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:10] Reserved reset value.
  • Page 176 ISD94100 Series Technical Reference Manual Power Manager Control Register (CLK_PMUCTL) Offset R/W Description Reset Value Register CLK_PMUCTL CLK_BA+0x90 R/W Power Manager Control Register 0x0000_0080 Reserved RTCWKEN Reserved BODSPWK Reserved WKPINEN Reserved WKTMRIS WKTMREN Reserved PDMSEL Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:24] Reserved reset value.
  • Page 177 ISD94100 Series Technical Reference Manual Wake-up Timer Time-out Interval Select (Write Protected) This is a protected register. Please refer to open lock sequence to program it. These bits control wake-up timer time-out interval when chip at DPD/SPD mode. 000 = Time-out interval is 128 LIRC clocks (About 12.8 ms). 001 = Time-out interval is 256 LIRC clocks (About 25.6 ms).
  • Page 178 ISD94100 Series Technical Reference Manual Power Manager Status Register (CLK_PMUSTS) Offset R/W Description Reset Value Register CLK_PMUSTS CLK_BA+0x94 R/W Power Manager Status Register 0x0000_0001 CLRWK Reserved Reserved Reserved GPDWK GPCWK GPBWK GPAWK DPD_RSTWK SPD_TMRWK RTCWK BODWK Reserved DPD_TMRWK PINWK PORWK Description Bits Clear Wake-up Flag...
  • Page 179 ISD94100 Series Technical Reference Manual This flag indicates that wakeup of device from Standby Power-down mode was requested with a RTC alarm or tick time happened. This flag is cleared when SPD mode is entered. BOD Wake-up Flag (Read Only) BODWK This flag indicates that wakeup of device from Standby Power-down mode was requested with a BOD happened.
  • Page 180 ISD94100 Series Technical Reference Manual Chip LDO Register (CLK_LDOCTL) Offset R/W Description Reset Value Register CLK_LDOCTL CLK_BA+0x98 R/W Chip LDO Control Register 0x0000_0000 Reserved Reserved Reserved OVEN Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 181 ISD94100 Series Technical Reference Manual Standby Power-down Wake-up De-bounce Control Register (CLK_SWKDBCTL) Offset R/W Description Reset Value Register Standby Power-down Wake-up De-bounce Control CLK_SWKDBCTL CLK_BA+0x9C 0x0000_0000 Register Reserved Reserved Reserved Reserved SWKDBCLKSEL Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:4] Reserved reset value.
  • Page 182 ISD94100 Series Technical Reference Manual PA Standby Power-down Wake-up Control Register (CLK_PASWKCTL) Offset R/W Description Reset Value Register CLK_PASWKCTL CLK_BA+0xA0 R/W GPA Standby Power-down Wakeup Control Register 0x0000_0000 Reserved Reserved Reserved DBEN WKPSEL Reserved PFWKEN PRWKEN WKEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 183 ISD94100 Series Technical Reference Manual 1111 = PA.15 wake-up function enabled. Reserved. Any values read should be ignored. When writing to this field always write with Reserved reset value. Pin Falling Edge Wake-up Enable Bit PFWKEN 0 = PA group pin falling edge wake-up function disabled. 1 = PA group pin falling edge wake-up function enabled.
  • Page 184 ISD94100 Series Technical Reference Manual PB Standby Power-down Wake-up Control Register (CLK_PBSWKCTL) Offset R/W Description Reset Value Register CLK_PBSWKCTL CLK_BA+0xA4 R/W GPB Standby Power-down Wakeup Control Register 0x0000_0000 Reserved Reserved Reserved DBEN WKPSEL Reserved PFWKEN PRWKEN WKEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 185 ISD94100 Series Technical Reference Manual 1111 = PB.15 wake-up function enabled. Reserved. Any values read should be ignored. When writing to this field always write with Reserved reset value. Pin Falling Edge Wake-up Enable Bit PFWKEN 0 = PB group pin falling edge wake-up function disabled. 1 = PB group pin falling edge wake-up function enabled.
  • Page 186 ISD94100 Series Technical Reference Manual PC Standby Power-down Wake-up Control Register (CLK_PCSWKCTL) Offset R/W Description Reset Value Register CLK_PCSWKCTL CLK_BA+0xA8 R/W GPC Standby Power-down Wakeup Control Register 0x0000_0000 Reserved Reserved Reserved DBEN WKPSEL Reserved PFWKEN PRWKEN WKEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 187 ISD94100 Series Technical Reference Manual 1111 = PC.15 wake-up function enabled. Reserved. Any values read should be ignored. When writing to this field always write with Reserved reset value. Pin Falling Edge Wake-up Enable Bit PFWKEN 0 = PC group pin falling edge wake-up function disabled. 1 = PC group pin falling edge wake-up function enabled.
  • Page 188 ISD94100 Series Technical Reference Manual PD Standby Power-down Wake-up Control Register (CLK_PDSWKCTL) Offset R/W Description Reset Value Register CLK_PDSWKCTL CLK_BA+0xAC R/W GPD Standby Power-down Wakeup Control Register 0x0000_0000 Reserved Reserved Reserved DBEN WKPSEL Reserved PFWKEN PRWKEN WKEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 189 ISD94100 Series Technical Reference Manual 1111 = PD.15 wake-up function enabled. Reserved. Any values read should be ignored. When writing to this field always write with Reserved reset value. Pin Falling Edge Wake-up Enable Bit PFWKEN 0 = PD group pin falling edge wake-up function disabled. 1 = PD group pin falling edge wake-up function enabled.
  • Page 190 ISD94100 Series Technical Reference Manual GPIO Standby Power-down Control Register (CLK_IOPDCTL) Offset R/W Description Reset Value Register CLK_IOPDCTL CLK_BA+0xB0 R/W GPIO Standby Power-down Control Register 0x0000_0000 Reserved Reserved Reserved Reserved IOHR Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:1] Reserved reset value.

  • Page 191: Flash Memory Controller (Fmc)

    ISD94100 Series Technical Reference Manual Flash Memory Controller (FMC) 6.4.1 Overview The ISD94100 Series provides up to 512 KB of on-chip embedded flash for application program memory (APROM) and data flash. In-System-Programming (ISP) and In-Application-Programming (IAP) enables user to update chip embedded flash when chip is soldered on PCB. After chip ®...

  • Page 192: Block Diagram

    ISD94100 Series Technical Reference Manual 6.4.3 Block Diagram The flash memory controller consists of AHB slave interface, ISP control logic and flash macro interface timing control logic. The block diagram of flash memory controller is shown as follows. Cortex-M4 S-BUS Cortex-M4 I-BUS / D-BUS Flash Memory Controller AHB Slave Interface...
  • Page 193 ISD94100 Series Technical Reference Manual AHB Slave Interface ® There are two AHB slave interfaces in the flash memory controller, one is from both Cortex I-Bus and D-Bus for instruction and data fetch; the other is from Cortex ® -M4 S-Bus for flash control registers access, including ISP registers.

  • Page 194: Functional Description

    ISD94100 Series Technical Reference Manual 6.4.4 Functional Description This section describes ISD94100 series flash memory controller’s functions including memory organization, boot configuration, IAP, ISP, Flash read/write operation, checksum calculation, and so on. 6.4.4.1 Memory Organization 0x0030_000B Configuration Configure: security lock, boot select, brown-out voltage, data Bytes 0x0030_0000...

  • Page 195: Table 6.4.4-1 Flash Memory Address Map

    ISD94100 Series Technical Reference Manual LDROM LDROM is designed for a loader to implement In-System-Programming (ISP) function. It is a 4 KB size flash memory region, the range of address from 0x0010_0000 to 0x0010_0FFF. Configuration Bytes The ISD94100 device provides 3-words of flash memory, from address 0x0030_0000 to store system configuration such as logic, flash security lock, boot select, brown-out voltage level, Data Flash base address, etc.

  • Page 196: Figure 6.4-4 Boot From Ldrom With Iap Support

    ISD94100 Series Technical Reference Manual CBS[1:0] Running mode Load System Vector table from Support Vector Re-Mapping LDROM with IAP 0x0010_0000 - 0x0010_01FF LDROM without IAP 0x0010_0000 - 0x0010_01FF APROM with IAP 0x0000_0000 - 0x0010_01FF APROM without IAP 0x0000_0000 - 0x0010_01FF Table 6.4.4-2 Boot Configuration 6.4.4.2.1 Boot from LDROM with IAP support...

  • Page 197: Figure 6.4-5 Boot From Aprom With Iap Support

    ISD94100 Series Technical Reference Manual 6.4.4.2.2 Boot from APROM with IAP support By writing 0b10 into CBS[1:0] bits in CONFIG0, the ISD94100 device will load the system vector table from APROM space 0x0000_0000 - 0x0000_01FF. In this mode, except that the MCU boots from APROM, all other functions as the same as “boot from LDROM with IAP support”...

  • Page 198: Figure 6.4-6 Boot From Ldrom Without Iap Support

    ISD94100 Series Technical Reference Manual Reserved 0x0010_0FFF Loader ROM (LDROM 4KB) 0x0010_0200 0x0010_01FF Vector Table 0x0010_0000 Reserved 0x0007_FFFF Reserved 0x0000_0200 0x0000_01FF System Vector Table 0x0000_0000 Figure 6.4-6 Boot from LDROM without IAP support This mode does not support IAP -- because it cannot access APROM, and the LDROM has only 4 KB –...
  • Page 199 ISD94100 Series Technical Reference Manual In this mode the device can read, erase or write part of the APROM (or data flash). This mode does not support remapping function. 6.4.4.3 In-Application-Programming (IAP) The ISD94100 series provides In-Application-Programming (IAP) function for user to switch the system memory vector code executing between APROM and LDROM.
  • Page 200 ISD94100 Series Technical Reference Manual Programming Data FMC_MPDAT2~FMC_MPDAT3: FMC_ISPDAT :N/A FMC_MPDAT0: 1’st Programming Data FMC_MPDAT1: 2’nd Valid address of flash memory organization in APROM, Multi-Word Program 0x27 Programming Data LDROM FMC_MPDAT2: 3’rd Programming Data FMC_MPDAT3: 4’th Programming Data FMC_ISPDAT: Return Data FLASH Read 0x00 Valid address of flash memory organization...

  • Page 201: Figure 6.4-8 Isp Procedure Example

    ISD94100 Series Technical Reference Manual FMC_MPDAT0~FMC_MPDAT3 : FMC_ISPDAT: Unique ID Word 2 0x0000_0008 FMC_MPDAT0~FMC_MPDAT3 : Valid address in APROM,LDROM or boot loader Vector Remap 0x2E It must be 512 bytes alignment Table 6.4.4-3 ISP Command List ISP Procedure The FMC controller supports flash memory read, erase and re-programming functions. Some control bits or ISP registers are write-protected, and require unlock and lock sequence before and after access.

  • Page 202: Table 6.4.4-4 Fmc Control Registers For Flash Read/Write

    ISD94100 Series Technical Reference Manual period; the peripheral still keeps working as usual. If any interrupt request occurs, CPU will not service it until ISP operation is finished. When ISP operation is finished, the ISPGO bit will be cleared by hardware automatically. Software can poll ISPGO bit to determine whether ISP operation is finished.

  • Page 203: Figure 6.4-9 Flash 32-Bit Write Procedure

    ISD94100 Series Technical Reference Manual 32-bit Read The code snippet below show how to do 32-bit read: FMC->ISPCMD = FMC_ISPCMD_READ; // op code for 32-bit read is 0x00 FMC->ISPADDR = u32Addr; // the flash memory address where read from FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; // set ISPGO bit to start reading ...

  • Page 204: Figure 6.4-10 Flash 64-Bit Write Procedure

    ISD94100 Series Technical Reference Manual Code snippet for 32_bit flash write: FMC->ISPCMD = FMC_ISPCMD_PROGRAM; // op code for 32-bit write is 0x21 FMC->ISPCTL &= ~(7<<8); // Set PT = 0 FMC->ISPADDR = u32Addr; FMC->ISPDAT = u32Data; FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ; // Check ISPFF flag (FMC_ISPCTL[6]) 64-bit Write Figure 6.4-10 illustrates the operation flow of 64-bit flash write.

  • Page 205: Figure 6.4-11 Timeline Comparison For Write Operations

    ISD94100 Series Technical Reference Manual multi-word write operation needs to write at least 16 bytes (4 words), and can write up to 512 bytes. No matter how many bytes are to be written in one multi-word write session, there is only one flash SETUP time before writing and only one HOLD time after writing, as shown in Figure 6.4-11 below.
  • Page 206 ISD94100 Series Technical Reference Manual The multi-word programming flow is shown in Figure 6.4-13. The starting ISP address (FMC_ISPADDR) has to be 16-byte align, FMC_ISPADDR[3:0] should be 0. FMC_MPDAT0 is the data word of the offset 0x0, FMC_MPDAT1 is the second word (offset 0x4), FMC_MPDAT2 is the third word (offset 0x8), and FMC_MPDAT3 is forth word (offset 0xC).

  • Page 207: Figure 6.4-13 Multi-Word Programming Flow Chart

    ISD94100 Series Technical Reference Manual Start Enable ISPEN Set PT Write FMC_ISPCMD Write FMC_ISPADDR Write FMC_MPDAT0 Write FMC_MPDAT1 Write FMC_MPDAT2 Write FMC_MPDAT3 Set ISPGO = 1 Programming Finish? Read FMC_MPSTS Read FMC_MPSTS Read FMC_MPADDR Check MPBUSY==0? (D1,D0)=00? MPBUSY == 0? Write FMC_MPDAT0 Write FMC_MPDAT1 End of ISP...

  • Page 208: Figure 6.4-14 Fast Flash Programming Verification Flow

    ISD94100 Series Technical Reference Manual 6.4.4.6 Fast Flash Programming Verification The ISD94100 series supports fast flash programming with hardware self-verification feature, in which during programming the hardware does verification at the same time, so that it saves time for memory data read back and comparison. That is, when data is programmed to the embedded flash memory, the controller asserts the flash read operation to read data out, and performs data comparison.

  • Page 209: Figure 6.4-15 Verification Flow

    ISD94100 Series Technical Reference Manual Traditional (2) Flash PROGRAM (3) Flash READ back to check Programming and (1) Flash ERASE (All datas) (All datas) Verification Flow I94100 (2) Flash PROGRAM (3) Read PGFF Flag to check Fast Programming (1) Flash ERASE (All datas) (FMC_ISPSTS) Verification Flow...
  • Page 210 ISD94100 Series Technical Reference Manual Three steps complete this CRC32 checksum calculation. Step 1: perform ISP “Run Memory CRC32 Checksum” operation Step 2: perform ISP “Read Memory CRC32 Checksum” operation Step 3: read FMC_ISPDAT to get checksum. In step 1, user has to set the memory starting address (FMC_ISPADDR) and size (FMC_ISPDAT) to calculate.
  • Page 211 ISD94100 Series Technical Reference Manual while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) ; Sep 9, 2019 Page 211 of 928 Rev1.09...

  • Page 212: Table 6.4.4-5 Flash Access Optimized Cycle Under Auto-Tuning Function

    ISD94100 Series Technical Reference Manual 6.4.4.9 Flash Access Cycle Auto-Tuning The ISD94100 series supports the flash access cycle auto-tuning function. User don’t need to set the flash access cycle by manual while system clock (HCLK) is changed, hardware will monitor the HCLK frequency and generate a optimized cycle number for flash controller to get the best performance.

  • Page 213: Figure 6.4-17 Flash Access Cycle Auto-Tuning Flow

    ISD94100 Series Technical Reference Manual Flash access cycle Auto-tuning Enabled Auto-tuning Trigger Event? Set Flash Access Cycle = 8 HIRC clock stable ? New clock Stable? HCLK counting in a fix period Generate the optimized access cycle number Set Flash Access Cycle The optimized access cycle number Figure 6.4-17 Flash access cycle auto-tuning flow...

  • Page 214: Table 6.4.4-6 The Lock Effect Table With Two Protections

    ISD94100 Series Technical Reference Manual LOCK2, LOCK (CONFIG0[2:1]) CPU, via user code present in APROM/LDROM, can erase/program/read flash memory via ISP registers, can modify registers and SRAM Accept ICP mass erase command SWD/ICE can use page erase/program/read flash memory by ICP SWD/ICE can use page erase/program/read flash memory via ISP registers, can modify registers and SRAM...

  • Page 215: Register Map

    ISD94100 Series Technical Reference Manual 6.4.5 Register Map R: read only, W: write only, R/W: both read and write Configuration Offset R/W Description Reset Value Bytes Configuration Bytes Base Address: FMC_CONFIG_BASE = 0x0030_0000 CONFIG0 FMC_CONFIG_BA+0x00 R/W Configuration byte 0x00 ~ 0x03 Flash, no change CONFIG1 FMC_CONFIG_BA+0x04...
  • Page 216 ISD94100 Series Technical Reference Manual The reserved register fields that listed in register description must be written to their reset value. Writing reserved fields with other than reset values may produce undefined results. Sep 9, 2019 Page 216 of 928 Rev1.09...

  • Page 217: Register Description

    ISD94100 Series Technical Reference Manual 6.4.6 Register Description CONFIG0 (Address = 0x0030_0000) CWDTEN[2] Reserved CFGXT1 CFOSC Reserved CBOV CBORST CBODEN Reserved Reserved GPA8_LOW CIOINI Reserved Reserved CWDTE[1:0] LOCK2 LOCK DFEN Bits Descriptions Watchdog Timer Hardware Enable Bit When watchdog timer hardware enable function is enabled, the watchdog enable bit WDTEN (WDT_CTL[7]) and watchdog reset enable bit RSTEN (WDT_CTL[1]) is set to 1 automatically after power on.
  • Page 218 ISD94100 Series Technical Reference Manual Brown-Out Reset Enable Bit CBORST [20] 0 = Brown-out reset Enabled after power on. 1 = Brown-out reset Disabled after power on. Brown-Out Detector Enable Bit [19] CBODEN 0 = Brown-out detect Enabled after powered on. 1 = Brown-out detect Disabled after power on.
  • Page 219 ISD94100 Series Technical Reference Manual Data Flash Enable Bit The Data Flash is shared with APROM, and the base address of Data Flash is decided by DFBA (CONFIG1[19:0]) when DFEN is 0. DFEN 0 = Data Flash Enabled. 1 = Data Flash Disabled. Note: The bits of configure should be 1 if reserved.
  • Page 220 ISD94100 Series Technical Reference Manual CONFIG1 (Address = 0x0030_0004) Reserved Reserved DFBA DFBA DFBA Bits Descriptions [31:20] Reserved Reserved bit should always be programmed with 0. Data Flash Base Address This register works only when DFEN (CONFIG0[0])set to 0. If DFEN (CONFIG0[0]) is set to DFBA [19:0] 0, the Data Flash base address is defined by user.
  • Page 221 ISD94100 Series Technical Reference Manual CONFIG2 (Address = 0x0030_0008) Reserved Reserved ALOCK ALOCK Bits Descriptions [31:16] Reserved Reserved bit should always be programmed with 1. Advance Security Lock Control Must be set to 0x5A5A for access to flash memory content. Any other value, flash memory is locked.
  • Page 222 ISD94100 Series Technical Reference Manual ISP Control Register (FMC_ISPCTL) Offset R/W Description Reset Value Register FMC_ISPCTL FMC_BA+0x00 R/W ISP Control Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPFF LDUEN CFGUEN APUEN Reserved ISPEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:11] Reserved reset value.
  • Page 223 ISD94100 Series Technical Reference Manual Boot Select (Write Protected) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened 0 = Boot from APROM.
  • Page 224 ISD94100 Series Technical Reference Manual ISP Address (FMC_ISPADDR) Offset R/W Description Reset Value Register FMC_ISPADDR FMC_BA+0x04 R/W ISP Address Register 0x0000_0000 ISPADDR ISPADDR ISPADDR ISPADDR Description Bits ISP Address The ISD94100 series is equipped with an embedded . ISPADDR[1:0] must be kept 00 for ISP 32-bit operation.
  • Page 225 ISD94100 Series Technical Reference Manual ISP Data Register (FMC_ISPDAT) Offset R/W Description Reset Value Register FMC_ISPDAT FMC_BA+0x08 R/W ISP Data Register 0x0000_0000 ISPDAT ISPDAT ISPDAT ISPDAT Description Bits ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation. [31:0] ISPDAT When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff.
  • Page 226 ISD94100 Series Technical Reference Manual ISP Command Register (FMC_ISPCMD) Offset R/W Description Reset Value Register FMC_ISPCMD FMC_BA+0x0C R/W ISP Command Register 0x0000_0000 Reserved Reserved Reserved Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with reset [31:7] Reserved value.
  • Page 227 ISD94100 Series Technical Reference Manual ISP Trigger Control Register (FMC_ISPTRG) Offset R/W Description Reset Value Register FMC_ISPTRG FMC_BA+0x10 R/W ISP Trigger Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPGO Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:1] Reserved reset value.
  • Page 228 ISD94100 Series Technical Reference Manual Data Flash Base Address Register (FMC_DFBA) Offset R/W Description Reset Value Register FMC_DFBA FMC_BA+0x14 Data Flash Base Address 0xXXXX_XXXX DFBA DFBA DFBA DFBA Description Bits Data Flash Base Address This register indicates Data Flash start address. It is a read only register. [31:0] DFBA The Data Flash is shared with APROM.
  • Page 229 ISD94100 Series Technical Reference Manual ISP Status Register (FMC_ISPSTS) Offset R/W Description Reset Value Register FMC_ISPSTS FMC_BA+0x40 ISP Status Register 0x0000_000X Reserved VECMAP VECMAP Reserved ALLONE ISPFF PGFF FCYCDIS Reserved ISPBUSY Bits Description Reserved. Any values read should be ignored. When writing to this field always write with Reserved [31:24] reset value.
  • Page 230 ISD94100 Series Technical Reference Manual Reserved. Any values read should be ignored. When writing to this field always write with Reserved reset value. Chip Boot Selection Mode (Read Only) This CBS field is just a copy of flash controller user configuration register CBS (CONFIG0 [2:1] [7:6]).
  • Page 231 ISD94100 Series Technical Reference Manual Flash Access Cyce Control Register (FMC_CYCCTL) Offset R/W Description Reset Value Register FMC_CYCCTL FMC_BA+0x4C R/W Flash Access Cycle Control Register 0x0001_0000 Reserved Reserved Reserved FADIS Reserved CYCLE Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 232 ISD94100 Series Technical Reference Manual Flash Access Cycle Control (Write Protect) This register is updated automaticly by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCCTL[8]) is 0000 = CPU access with zero wait cycle ; flash access cycle is 1;. The HCLK working frequency range is <27 MHz;...
  • Page 233 ISD94100 Series Technical Reference Manual ISP Data 0 Register (FMC_MPDAT0) Offset R/W Description Reset Value Register FMC_MPDAT0 FMC_BA+0x80 R/W ISP Multi-Word Program Data0 Register 0x0000_0000 ISPDAT0 ISPDAT0 ISPDAT0 ISPDAT0 Description Bits ISP Data 0 [31:0] ISPDAT0 This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
  • Page 234 ISD94100 Series Technical Reference Manual ISP Data 1 Register (FMC_MPDAT1) Offset R/W Description Reset Value Register FMC_MPDAT1 FMC_BA+0x84 R/W ISP Multi-Word Program Data1 Register 0x0000_0000 ISPDAT1 ISPDAT1 ISPDAT1 ISPDAT1 Description Bits ISP Data 1 [31:0] ISPDAT1 This register is the second 32-bit data for 64-bit/multi-word programming. Sep 9, 2019 Page 234 of 928 Rev1.09...
  • Page 235 ISD94100 Series Technical Reference Manual ISP Data 2 Register (FMC_MPDAT2) Offset R/W Description Reset Value Register FMC_MPDAT2 FMC_BA+0x88 R/W ISP Multi-Word Program Data2 Register 0x0000_0000 ISPDAT2 ISPDAT2 ISPDAT2 ISPDAT2 Description Bits ISP Data 2 [31:0] ISPDAT2 This register is the third 32-bit data for multi-word programming. Sep 9, 2019 Page 235 of 928 Rev1.09...
  • Page 236 ISD94100 Series Technical Reference Manual ISP Data 3 Register (FMC_MPDAT3) Offset R/W Description Reset Value Register FMC_MPDAT3 FMC_BA+0x8C R/W ISP Multi-Word Program Data3 Register 0x0000_0000 ISPDAT3 ISPDAT3 ISPDAT3 ISPDAT3 Description Bits ISP Data 3 [31:0] ISPDAT3 This register is the fourth 32-bit data for multi-word programming. Sep 9, 2019 Page 236 of 928 Rev1.09...
  • Page 237 ISD94100 Series Technical Reference Manual ISP Multi-Program Status Register (FMC_MPSTS) Offset R/W Description Reset Value Register FMC_MPSTS FMC_BA+0xC0 ISP Multi-Word Program Status Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPFF PPGO MPBUSY Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:8] Reserved reset value.
  • Page 238 ISD94100 Series Technical Reference Manual ISP Fail Flag (Read Only) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0.
  • Page 239 ISD94100 Series Technical Reference Manual ISP Multi-Word Program Address Register (FMC_MPADDR) Offset R/W Description Reset Value Register FMC_MPADDR FMC_BA+0xC4 ISP Multi-Word Program Address Status Register 0x0000_0000 MPADDR MPADDR MPADDR MPADDR Description Bits ISP Multi-word Program Address [31:0] MPADDR MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. MPADDR will keep the final ISP address when ISP multi-word program is complete.

  • Page 240: General Purpose I/O (Gpio)

    ISD94100 Series Technical Reference Manual General Purpose I/O (GPIO) 6.5.1 Overview The ISD94100 series device has up to 58 General Purpose I/O (GPIO) pins, grouped in 4 ports PA, PB, PC and PD. Port PA, PC and PD each has 16 pins, and there are 13 pins in Port PB. All the GPIO pins are multi-functional pins, in that they can be I/O pins or they can work as alternate function pins.

  • Page 241: Basic Configuration

    ISD94100 Series Technical Reference Manual Control Registers PA[15:0] PB[15:13/9:0] PA[15:0] PC[15:0] Control Register PD[15:0] PB[15:13/9:0] Control Register PC[15:0] Control Register PD[15:0] Control Register Interrupt, Wake-up Event De-bounce Control Register Detector GPIO_INT Figure 6.5-1 GPIO Controller Block Diagram 6.5.4 Basic Configuration ...

  • Page 242: Functional Description

    ISD94100 Series Technical Reference Manual 6.5.5 Functional Description 6.5.5.1 Input Mode Writing 0b00 into MODEn bits (Px_MODE[2n+1:2n]) puts the corresponding Px.n pin in Input mode, and the pin will be in tri-state (high impedance). The input pin’s status is reflected in PX PIN[n] bit. For example if PA.0 is an input pin, the input level can be read by reading PA_PIN register, and PA_PIN[0] has the input value for PA.0 pin.

  • Page 243: Figure 6.5-3 Open-Drain Output

    ISD94100 Series Technical Reference Manual Figure 6.5-3 Open-Drain Output 6.5.5.4 Quasi-bidirectional Mode Writing 0b11 to MODEn bits (Px_MODE[2n+1:2n]) configures the corresponding Px.n pin as Quasi- bidirectional mode I/O pin. Under this mode, the I/O pin supports digital output and input function at the same time however the max source current is only less than 100uA.

  • Page 244: Figure 6.5-5 Gpio Rising Edge Trigger Interrupt

    ISD94100 Series Technical Reference Manual Figure 6.5-5 shows the triggering condition for a GPIO rising edge trigger interrupt. The interval of time between the two valid sample signal is determined by DBCLKSRC (Px_DBCTL[4]) and DBCLKSEL (Px_DBCTL[3:0]). Each valid data from GPIO pin need to be sampled twice. For rising edge trigger: ...

  • Page 245: Figure 6.5-6 Gpio Falling Edge Trigger Interrupt

    ISD94100 Series Technical Reference Manual Figure 6.5-6 GPIO Falling Edge Trigger Interrupt Table 6.5.5-1 shows the pre-condition for de-bounce support. System Status DBEN DBCLKSRC Description No de-bounce function No de-bounce function Normal Mode / Idle Mode De-bounce function using HCLK De-bounce function using LIRC (10 kHz) No de-bounce function No de-bounce function...

  • Page 246: Register Map

    ISD94100 Series Technical Reference Manual 6.5.6 Register Map R: read only, W: write only, R/W: both read and write. Offset R/W Description Reset Value Register GPIO Base Address: GPIO_BA = 0x4000_4000 PA_MODE GPIO_BA+0x000 R/W PA I/O Mode Control 0xXXXX_XXXX PA_DINOFF GPIO_BA+0x004 R/W PA Digital Input Path Disable Control 0x0000_0000...
  • Page 247 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register GPIO Base Address: GPIO_BA = 0x4000_4000 PC_INTTYPE GPIO_BA+0x098 R/W PC Interrupt Trigger Type Control 0x0000_0000 PC_INTEN GPIO_BA+0x09C R/W PC Interrupt Enable Control Register 0x0000_0000 PC_INTSRC GPIO_BA+0x0A0 R/W PC Interrupt Source Flag 0x0000_0000 PC_SMTEN GPIO_BA+0x0A4...

  • Page 248: Register Description

    ISD94100 Series Technical Reference Manual 6.5.7 Register Description Port A-D I/O Mode Control (Px_MODE) Offset R/W Description Reset Value Register PA_MODE GPIO_BA+0x000 R/W PA I/O Mode Control 0xXXXX_XXXX PB_MODE GPIO_BA+0x040 R/W PB I/O Mode Control 0xXX0X_XXXX PC_MODE GPIO_BA+0x080 R/W PC I/O Mode Control 0xXXXX_XXXX PD_MODE GPIO_BA+0x0C0...
  • Page 249 ISD94100 Series Technical Reference Manual Port A-D Digital Input Path Disable Control (Px_DINOFF) Offset R/W Description Reset Value Register PA_DINOFF GPIO_BA+0x004 R/W PA Digital Input Path Disable Control 0x0000_0000 PB_DINOFF GPIO_BA+0x044 R/W PB Digital Input Path Disable Control 0x0000_0000 PC_DINOFF GPIO_BA+0x084 R/W PC Digital Input Path Disable Control 0x0000_0000...
  • Page 250 ISD94100 Series Technical Reference Manual Port A-D Data Output Value (Px_DOUT) Offset R/W Description Reset Value Register PA_DOUT GPIO_BA+0x008 R/W PA Data Output Value 0x0000_FXFF PB_DOUT GPIO_BA+0x048 R/W PB Data Output Value 0x0000_F3FF PC_DOUT GPIO_BA+0x088 R/W PC Data Output Value 0x0000_FFFF PD_DOUT GPIO_BA+0x0C8...
  • Page 251 ISD94100 Series Technical Reference Manual Port A-D Data Output Write Mask (Px_DATMSK) Offset R/W Description Reset Value Register PA_DATMSK GPIO_BA+0x00C R/W PA Data Output Write Mask 0x0000_0000 PB_DATMSK GPIO_BA+0x04C R/W PB Data Output Write Mask 0x0000_0000 PC_DATMSK GPIO_BA+0x08C R/W PC Data Output Write Mask 0x0000_0000 PD_DATMSK GPIO_BA+0x0CC...
  • Page 252 ISD94100 Series Technical Reference Manual Port A-D Pin Value (Px_PIN) Offset R/W Description Reset Value Register PA_PIN GPIO_BA+0x010 PA Pin Value 0x0000_XXXX PB_PIN GPIO_BA+0x050 PB Pin Value 0x0000_XXXX PC_PIN GPIO_BA+0x090 PC Pin Value 0x0000_XXXX PD_PIN GPIO_BA+0x0D0 PD Pin Value 0x0000_XXXX Reserved Reserved Description...
  • Page 253 ISD94100 Series Technical Reference Manual Port A-D De-bounce Enable Control Register (Px_DBEN) Offset R/W Description Reset Value Register PA_DBEN GPIO_BA+0x014 R/W PA De-Bounce Enable Control Register 0x0000_0000 PB_DBEN GPIO_BA+0x054 R/W PB De-Bounce Enable Control Register 0x0000_0000 PC_DBEN GPIO_BA+0x094 R/W PC De-Bounce Enable Control Register 0x0000_0000 PD_DBEN GPIO_BA+0x0D4...
  • Page 254 ISD94100 Series Technical Reference Manual Port A-D Interrupt Type Control (Px_INTTYPE) Offset R/W Description Reset Value Register PA_INTTYPE GPIO_BA+0x018 R/W PA Interrupt Trigger Type Control 0x0000_0000 PB_INTTYPE GPIO_BA+0x058 R/W PB Interrupt Trigger Type Control 0x0000_0000 PC_INTTYPE GPIO_BA+0x098 R/W PC Interrupt Trigger Type Control 0x0000_0000 PD_INTTYPE GPIO_BA+0x0D8...
  • Page 255 ISD94100 Series Technical Reference Manual Port A-D Interrupt Enable Control Register (Px_INTEN) Offset R/W Description Reset Value Register PA_INTEN GPIO_BA+0x01C R/W PA Interrupt Enable Control Register 0x0000_0000 PB_INTEN GPIO_BA+0x05C R/W PB Interrupt Enable Control Register 0x0000_0000 PC_INTEN GPIO_BA+0x09C R/W PC Interrupt Enable Control Register 0x0000_0000 PD_INTEN GPIO_BA+0x0DC...
  • Page 256 ISD94100 Series Technical Reference Manual Max. n=15 for port A/C/D n=0..9, 13, 14, 15 for port B Sep 9, 2019 Page 256 of 928 Rev1.09...
  • Page 257 ISD94100 Series Technical Reference Manual Port A-D Interrupt Source Flag (Px_INTSRC) Offset R/W Description Reset Value Register PA_INTSRC GPIO_BA+0x020 R/W PA Interrupt Source Flag 0x0000_0000 PB_INTSRC GPIO_BA+0x060 R/W PB Interrupt Source Flag 0x0000_0000 PC_INTSRC GPIO_BA+0x0A0 R/W PC Interrupt Source Flag 0x0000_0000 PD_INTSRC GPIO_BA+0x0E0...
  • Page 258 ISD94100 Series Technical Reference Manual Port A-D Input Schmitt Trigger Enable Register (Px_SMTEN) Offset R/W Description Reset Value Register PA_SMTEN GPIO_BA+0x024 R/W PA Input Schmitt Trigger Enable Register 0x0000_0000 PB_SMTEN GPIO_BA+0x064 R/W PB Input Schmitt Trigger Enable Register 0x0000_0000 PC_SMTEN GPIO_BA+0x0A4 R/W PC Input Schmitt Trigger Enable Register 0x0000_0000...
  • Page 259 ISD94100 Series Technical Reference Manual Port A-D High Slew Rate Control Register (Px_SLEWCTL) Offset R/W Description Reset Value Register PA_SLEWCTL GPIO_BA+0x028 R/W PA High Slew Rate Control Register 0x0000_0000 PB_SLEWCTL GPIO_BA+0x068 R/W PB High Slew Rate Control Register 0x0000_0000 PC_SLEWCTL GPIO_BA+0x0A8 R/W PC High Slew Rate Control Register 0x0000_0000...
  • Page 260 ISD94100 Series Technical Reference Manual Port A-D Pull-up and Pull-down Selection Register (Px_PUSEL) Offset R/W Description Reset Value Register PA_PUSEL GPIO_BA+0x030 R/W PA Pull-up and Pull-down Selection Register 0x0000_0000 PB_PUSEL GPIO_BA+0x070 R/W PB Pull-up and Pull-down Selection Register 0x0000_0000 PC_PUSEL GPIO_BA+0x0B0 R/W PC Pull-up and Pull-down Selection Register 0x0000_0000...
  • Page 261 ISD94100 Series Technical Reference Manual Interrupt De-bounce Control Register (GPIO_DBCTL) Offset R/W Description Reset Value Register GPIO_DBCTL GPIO_BA+0x440 R/W Interrupt De-bounce Control Register 0x0000_0020 Reserved Reserved Reserved Reserved ICLKON DBCLKSRC DBCLKSEL Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:6] Reserved reset value.
  • Page 262 ISD94100 Series Technical Reference Manual Description Bits De-bounce Sampling Cycle Selection 0000 = Sample interrupt input once per 1 clocks. 0001 = Sample interrupt input once per 2 clocks. 0010 = Sample interrupt input once per 4 clocks. 0011 = Sample interrupt input once per 8 clocks. 0100 = Sample interrupt input once per 16 clocks.
  • Page 263 ISD94100 Series Technical Reference Manual GPIO Px.n Pin Data Input/Output Register (Pxn_PDIO) Offset R/W Description Reset Value Register PAn_PDIO GPIO_BA+0x800+ R/W GPIO PA.n Pin Data Input/Output Register 0x0000_000X (0x04 * n) n=0,1..15 PBn_PDIO GPIO_BA+0x840+ R/W GPIO PB.n Pin Data Input/Output Register 0x0000_000X (0x04 * n) n=0,1..9,13..15...

  • Page 264: Pdma Controller (Pdma)

    ISD94100 Series Technical Reference Manual 6.6 PDMA Controller (PDMA) 6.6.1 Overview The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer. The PDMA controller can transfer data from one address to another without CPU intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.

  • Page 265: Basic Configuration

    ISD94100 Series Technical Reference Manual 6.6.4 Basic Configuration  Clock source configuration – Enable PDMA controller clock in PDMACKEN (CLK_AHBCLK [1]).  Reset configuration – Reset PDMA controller in PDMARST (SYS_IPRST0[2]). 6.6.5 Functional Description The PDMA controller transfers data from one address to another without CPU intervention. The PDMA controller supports 16 independent channels and serves only one channel at one time, as the result, PDMA controller supports two level channel priorities: fixed and round-robin priority, PDMA controller serves channel in order from highest to lowest priority channel.

  • Page 266: Table 6.6.5-1 Channel Priority Table

    ISD94100 Series Technical Reference Manual is listed in Table 6.6.5-1. Channel Number Priority Setting Arbitration Priority In Descending Order PDMA_PRISET Channel15, Fixed Priority Highest Channel14, Fixed Priority Channel0, Fixed Priority Channel15, Round-Robin Priority Channel14, Round-Robin Priority Channel0, Round-Robin Priority Lowest Table 6.6.5-1 Channel Priority Table 6.6.5.2 PDMA Operation Mode...

  • Page 267: Figure 6.6-3 Basic Mode Finite State Machine

    ISD94100 Series Technical Reference Manual Transfer State OPMODE (PDMA_DSCTn_CTL[1:0]) = 0x1 Next Request Transfer done Idle State OPMODE (PDMA_DSCTn_CTL[1:0]) = 0x0 Figure 6.6-3 Basic Mode Finite State Machine Scatter-Gather Mode Scatter-Gather mode is a complex mode and can perform sophisticated transfer through the use of the description link list table as shown in Figure 6.6-4.

  • Page 268: Figure 6.6-4 Descriptor Table Link List Structure

    ISD94100 Series Technical Reference Manual PDMA_SCATBA DSCT15 DSCT_NEXT MSB 16 bits LSB 16 bits DSCT14 DSCT_DA without [1:0] DSCT_SA DSCT_CTL Current DSCT Entry DSCT_NEXT DSCT1 DSCT_DA DSCT0 DSCT_SA Load the information to the channel 15 descriptor table DSCT_CTL Next DSCT Entry SRAM Figure 6.6-4 Descriptor Table Link List Structure The above link list table operation is DSCT state in Scatter-Gather Mode as shown in Figure 6.6-5.
  • Page 269 ISD94100 Series Technical Reference Manual 6.6.5.3 Transfer Type The PDMA controller supports two transfer types: single transfer type and burst transfer type, configure by setting TXTYPE (PDMA_DSCTn_CTL[2]). When PDMA controller operated in single transfer type, each transfer data needs one request signal for one transfer, after transferred data, TXCNT (PDMA_DSCTn_CTL[31:16]) will decrease 1.

  • Page 270: Figure 6.6-6 Example Of Single Transfer Type And Burst Transfer Type In Basic Mode

    ISD94100 Series Technical Reference Manual Execution Channel 1 Channel 0 Channel 1 Channel 0 Channel Transferred Transferred CH1 Request 1 byte data 1 byte data Transferred Transferred CH0 Request 128 words data 128 words data TXCNT (PDMA_DSCTn_CTL[31:16]) TXWIDTH (PDMA_DSCTn_CTL[13:12]) (1 byte) (1 word) BURSIZE Non-useful...

  • Page 271: Figure 6.6-7 Example Of Pdma Channel 0 Time-Out Counter Operation

    ISD94100 Series Technical Reference Manual Time-out clock (HCLK/2^8) TOUTPSC0 (PDMA_TOUTPSC[2:0]) TOC0 (PDMA_TOC0_1[15:0]) 0 1 2 3 0 1 2 3 4 5 0 1 2 3 Time-out counter TOUTEN0 (PDMA_TOUTEN[0]) Peripheral request REQTOF0 (PDMA_INTSTS[8]) Figure 6.6-7 Example of PDMA Channel 0 Time-out Counter Operation 6.6.5.5 Stride Function The PDMA support channel 0 to channel 5 six channels with stride function.
  • Page 272 ISD94100 Series Technical Reference Manual 6.6.5.6 PDMA Controller Transfer Bandwidth The PDMA fits into the memory system of the ISD94100 as a master on the AHB bus. Only a finite number of PDMA transactions can occur on the AHB per second, hence there is a maximum bandwidth possible for PDMA transfers.

  • Page 273: Register Map

    ISD94100 Series Technical Reference Manual 6.6.6 Register Map R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register PDMA Base Address: PDMA_BA = 0x4000_8000 PDMA_DSCT0_CTL PDMA_BA + 0x00 R/W Descriptor Table Control Register of PDMA Channel 0 0xXXXX_XXXX PDMA_DSCT0_SA PDMA_BA + 0x04 R/W Source Address Register of PDMA Channel 0...
  • Page 274 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register PDMA Base Address: PDMA_BA = 0x4000_8000 R/W Descriptor Table Control Register of PDMA Channel 6 0xXXXX_XXXX PDMA_DSCT6_CTL PDMA_BA + 0x60 0xXXXX_XXXX PDMA_DSCT6_SA PDMA_BA + 0x64 R/W Source Address Register of PDMA Channel 6 0xXXXX_XXXX PDMA_DSCT6_DA PDMA_BA + 0x68...
  • Page 275 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register PDMA Base Address: PDMA_BA = 0x4000_8000 0xXXXX_XXXX PDMA_DSCT12_DA PDMA_BA + 0xC8 R/W Destination Address Register of PDMA Channel 12 First Scatter-Gather Descriptor Table Offset Address of 0xXXXX_XXXX PDMA_DSCT12_NEXT PDMA_BA + 0xCC PDMA Channel 12 R/W Descriptor Table Control Register of PDMA Channel 13 0xXXXX_XXXX PDMA_DSCT13_CTL...
  • Page 276 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register PDMA Base Address: PDMA_BA = 0x4000_8000 PDMA Channel 9 Current Scatter-Gather Descriptor Table Address of 0xXXXX_XXXX PDMA_CURSCAT10 PDMA_BA + 0x128 PDMA Channel 10 Current Scatter-Gather Descriptor Table Address of 0xXXXX_XXXX PDMA_CURSCAT11 PDMA_BA + 0x12C R...
  • Page 277 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register PDMA Base Address: PDMA_BA = 0x4000_8000 PDMA_REQSEL0_3 PDMA_BA + 0x480 R/W PDMA Request Source Select Register 0 0x0000_0000 PDMA_REQSEL4_7 PDMA_BA + 0x484 R/W PDMA Request Source Select Register 1 0x0000_0000 PDMA_REQSEL8_11 PDMA_BA + 0x488...

  • Page 278: Register Description

    ISD94100 Series Technical Reference Manual 6.6.7 Register Description Descriptor Table Control Register (PDMA_DSCTn_CTL) Offset R/W Description Reset Value Register PDMA_DSCT0_CTL PDMA_BA + 0x00 R/W Descriptor Table Control Register of PDMA Channel 0 0xXXXX_XXXX PDMA_DSCT1_CTL PDMA_BA + 0x10 R/W Descriptor Table Control Register of PDMA Channel 1 0xXXXX_XXXX PDMA_DSCT2_CTL PDMA_BA + 0x20...
  • Page 279 ISD94100 Series Technical Reference Manual Note: When PDMA finish each transfer data, this field will be decrease immediately. Stride Mode Enable Bit [15] STRIDEEN 0 = Stride transfer mode Disabled. 1 = Stride transfer mode Enabled. Reserved. Any values read should be ignored. When writing to this field always write with Reserved [14] Transfer Width Selection...
  • Page 280 ISD94100 Series Technical Reference Manual PDMA Operation Mode Selection 00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. 01 = Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[n] will be asserted.
  • Page 281 ISD94100 Series Technical Reference Manual Start Source Address Register (PDMA_DSCTn_SA) Offset R/W Description Reset Value Register PDMA_DSCT0_SA PDMA_BA + 0x04 R/W Source Address Register of PDMA Channel 0 0xXXXX_XXXX PDMA_DSCT1_SA PDMA_BA + 0x14 R/W Source Address Register of PDMA Channel 1 0xXXXX_XXXX PDMA_DSCT2_SA PDMA_BA + 0x24...
  • Page 282 ISD94100 Series Technical Reference Manual Destination Address Register (PDMA_DSCTn_DA) Offset R/W Description Reset Value Register PDMA_DSCT0_DA PDMA_BA + 0x08 R/W Destination Address Register of PDMA Channel 0 0xXXXX_XXXX PDMA_DSCT1_DA PDMA_BA + 0x18 R/W Destination Address Register of PDMA Channel 1 0xXXXX_XXXX PDMA_DSCT2_DA PDMA_BA + 0x28...
  • Page 283 ISD94100 Series Technical Reference Manual First Scatter-gather Descriptor Table Offset Address (PDMA_DSCTn_NEXT) Offset R/W Description Reset Value Register First Scatter-Gather Descriptor Table Offset Address of PDMA_DSCT0_NEXT PDMA_BA + 0x0C 0xXXXX_XXXX PDMA Channel 0 First Scatter-Gather Descriptor Table Offset Address of PDMA_DSCT1_NEXT PDMA_BA + 0x1C 0xXXXX_XXXX...
  • Page 284 ISD94100 Series Technical Reference Manual NEXT Description Bits PDMA Execution Next Descriptor Table Offset This field indicates the offset of next descriptor table address of current execution [31:16] EXENEXT descriptor table in system memory. Note: write operation is useless in this field. PDMA Next Descriptor Table Offset This field indicates the offset of the next descriptor table address in system memory.
  • Page 285 ISD94100 Series Technical Reference Manual Current Scatter-gather Descriptor Table Address (PDMA_CURSCATn) Offset R/W Description Reset Value Register Current Scatter-Gather Descriptor Table Address of PDMA_CURSCAT0 PDMA_BA + 0x100 0xXXXX_XXXX PDMA Channel 0 Current Scatter-Gather Descriptor Table Address of PDMA_CURSCAT1 PDMA_BA + 0x104 0xXXXX_XXXX PDMA Channel 1 Current Scatter-Gather Descriptor Table Address of...
  • Page 286 ISD94100 Series Technical Reference Manual Description Bits PDMA Current Description Address Register (Read Only) This field indicates a 32-bit current external description address of PDMA controller. [31:0] CURADDR Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
  • Page 287 ISD94100 Series Technical Reference Manual Channel Control Register (PDMA_CHCTL) Offset R/W Description Reset Value Register PDMA_CHCTL PDMA_BA + 0x400 R/W PDMA Channel Control Register 0x0000_0000 Reserved Reserved CHEN15 CHEN14 CHEN13 CHEN12 CHEN11 CHEN10 CHEN9 CHEN8 CHEN7 CHEN6 CHEN5 CHEN4 CHEN3 CHEN2 CHEN1 CHEN0...
  • Page 288 ISD94100 Series Technical Reference Manual Description Bits bit. PDMA Channel 11 Enable Bit Set this bit to 1 to enable PDMA channel 11 operation. Channel 11 cannot be active if it is not set as enabled. [11] CHEN11 0 = PDMA Channel 11 Disabled. 1 = PDMA Channel 11 Enabled.
  • Page 289 ISD94100 Series Technical Reference Manual Description Bits Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit. PDMA Channel 4 Enable Bit Set this bit to 1 to enable PDMA channel 4 operation. Channel 4 cannot be active if it is not set as enabled.
  • Page 290 ISD94100 Series Technical Reference Manual PDMA Transfer Stop Control Register (PDMA_STOP) Offset R/W Description Reset Value Register PDMA_STOP PDMA_BA + 0x404 PDMA Transfer Stop Control Register 0x0000_0000 Reserved Reserved STOP15 STOP14 STOP13 STOP12 STOP11 STOP10 STOP9 STOP8 STOP7 STOP6 STOP5 STOP4 STOP3 STOP2...
  • Page 291 ISD94100 Series Technical Reference Manual Description Bits PDMA Channel 11 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 11 transfer. When user sets STOP11 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN11 (PDMA_CHCTL [11]) and clear request active flag.
  • Page 292 ISD94100 Series Technical Reference Manual Description Bits User can set this bit to stop the PDMA channel 4 transfer. When user sets STOP4 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN4 (PDMA_CHCTL [4]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
  • Page 293 ISD94100 Series Technical Reference Manual PDMA Software Request Register (PDMA_SWREQ) Offset R/W Description Reset Value Register PDMA_SWREQ PDMA_BA + 0x408 PDMA Software Request Register 0x0000_0000 Reserved Reserved SWREQ15 SWREQ14 SWREQ13 SWREQ12 SWREQ11 SWREQ10 SWREQ9 SWREQ8 SWREQ7 SWREQ6 SWREQ5 SWREQ4 SWREQ3 SWREQ2 SWREQ1 SWREQ0...
  • Page 294 ISD94100 Series Technical Reference Manual Description Bits 0 = PDMA Channel 12 no effect. 1 = PDMA Channel 12 generate a software request. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
  • Page 295 ISD94100 Series Technical Reference Manual Description Bits 0 = PDMA Channel 6 no effect. 1 = PDMA Channel 6 generate a software request. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
  • Page 296 ISD94100 Series Technical Reference Manual Description Bits 0 = PDMA Channel 0 no effect. 1 = PDMA Channel 0 generate a software request. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
  • Page 297 ISD94100 Series Technical Reference Manual PDMA Channel Request Status Register (PDMA_TRGSTS) Offset R/W Description Reset Value Register PDMA_TRGSTS PDMA_BA + 0x40C R PDMA Channel Request Status Register 0x0000_0000 Reserved Reserved REQSTS15 REQSTS14 REQSTS13 REQSTS12 REQSTS11 REQSTS10 REQSTS9 REQSTS8 REQSTS7 REQSTS6 REQSTS5 REQSTS4 REQSTS3...
  • Page 298 ISD94100 Series Technical Reference Manual Description Bits This flag indicates whether channel 12 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. 0 = PDMA Channel 12 has no request. 1 = PDMA Channel 12 has a request.
  • Page 299 ISD94100 Series Technical Reference Manual Description Bits current transfer. PDMA Channel 6 Request Status (Read Only) This flag indicates whether channel 6 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
  • Page 300 ISD94100 Series Technical Reference Manual Description Bits 1 = PDMA Channel 1 has a request. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer. PDMA Channel 0 Request Status (Read Only) This flag indicates whether channel 0 have a request or not, no matter request from software or peripheral.
  • Page 301 ISD94100 Series Technical Reference Manual PDMA Fixed Priority Setting Register (PDMA_PRISET) Offset R/W Description Reset Value Register PDMA_PRISET PDMA_BA + 0x410 R/W PDMA Fixed Priority Setting Register 0x0000_0000 Reserved Reserved FPRISET15 FPRISET14 FPRISET13 FPRISET12 FPRISET11 FPRISET10 FPRISET9 FPRISET8 FPRISET7 FPRISET6 FPRISET5 FPRISET4 FPRISET3...
  • Page 302 ISD94100 Series Technical Reference Manual Description Bits 1 = Corresponding PDMA channel 13 is fixed priority. Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. PDMA Channel 12 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: 0 = No effect.
  • Page 303 ISD94100 Series Technical Reference Manual Description Bits 1 = Corresponding PDMA channel 8 is fixed priority. Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. PDMA Channel 7 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: 0 = No effect.
  • Page 304 ISD94100 Series Technical Reference Manual Description Bits 1 = Corresponding PDMA channel 3 is fixed priority. Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. PDMA Channel 2 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: 0 = No effect.
  • Page 305 ISD94100 Series Technical Reference Manual PDMA Fix Priority Clear Register (PDMA_PRICLR) Offset R/W Description Reset Value Register PDMA_PRICLR PDMA_BA + 0x414 PDMA Fixed Priority Clear Register 0x0000_0000 Reserved Reserved FPRICLR15 FPRICLR14 FPRICLR13 FPRICLR12 FPRICLR11 FPRICLR10 FPRICLR9 FPRICLR8 FPRICLR7 FPRICLR6 FPRICLR5 FPRICLR4 FPRICLR3 FPRICLR2...
  • Page 306 ISD94100 Series Technical Reference Manual Description Bits Note: User can read PDMA_PRISET register to know the channel priority. PDMA Channel 10 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. [10] FPRICLR10 0 = No effect. 1 = Clear PDMA channel 10 fixed priority setting.
  • Page 307 ISD94100 Series Technical Reference Manual Description Bits 0 = No effect. 1 = Clear PDMA channel 2 fixed priority setting. Note: User can read PDMA_PRISET register to know the channel priority. PDMA Channel 1 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level.
  • Page 308 ISD94100 Series Technical Reference Manual PDMA Interrupt Enable Register (PDMA_INTEN) Offset R/W Description Reset Value Register PDMA_INTEN PDMA_BA + 0x418 R/W PDMA Interrupt Enable Register 0x0000_0000 Reserved Reserved INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1...
  • Page 309 ISD94100 Series Technical Reference Manual Description Bits PDMA Channel 9 Interrupt Enable Register This field is used for enabling PDMA channel 9 interrupt. INTEN9 0 = PDMA channel 9 interrupt Disabled. 1 = PDMA channel 9 interrupt Enabled. PDMA Channel 8 Interrupt Enable Register This field is used for enabling PDMA channel 8 interrupt.
  • Page 310 ISD94100 Series Technical Reference Manual PDMA Interrupt Status Register (PDMA_INTSTS) Offset R/W Description Reset Value Register PDMA_INTSTS PDMA_BA + 0x41C R/W PDMA Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved REQTOF1 REQTOF0 Reserved TDIF ABTIF ALIGNF Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:10] Reserved reset value.
  • Page 311 ISD94100 Series Technical Reference Manual Description Bits 1 = AHB bus ERROR response received. Sep 9, 2019 Page 311 of 928 Rev1.09...
  • Page 312 ISD94100 Series Technical Reference Manual PDMA Channel Read/Write Target Abort Flag Register (PDMA_ABTSTS) Offset R/W Description Reset Value Register PDMA_ABTSTS PDMA_BA + 0x420 R/W PDMA Channel Read/Write Target Abort Flag Register 0x0000_0000 Reserved Reserved ABTIF15 ABTIF14 ABTIF13 ABTIF12 ABTIF11 ABTIF10 ABTIF9 ABTIF8 ABTIF7...
  • Page 313 ISD94100 Series Technical Reference Manual Description Bits PDMA Channel 10 Read/Write Target Abort Interrupt Status Flag This bit indicates PDMA channel 10 has target abort error; User can write 1 to clear these bits. [10] ABTIF10 0 = No AHB bus ERROR response received when channel 10 transfer. 1 = AHB bus ERROR response received when channel 10 transfer.
  • Page 314 ISD94100 Series Technical Reference Manual Description Bits This bit indicates PDMA channel 1 has target abort error; User can write 1 to clear these bits. 0 = No AHB bus ERROR response received when channel 1 transfer. 1 = AHB bus ERROR response received when channel 1 transfer. PDMA Channel 0 Read/Write Target Abort Interrupt Status Flag This bit indicates PDMA channel 0 has target abort error;...
  • Page 315 ISD94100 Series Technical Reference Manual PDMA Channel Transfer Done Flag Register (PDMA_TDSTS) Offset R/W Description Reset Value Register PDMA_TDSTS PDMA_BA + 0x424 R/W PDMA Channel Transfer Done Flag Register 0x0000_0000 Reserved Reserved TDIF15 TDIF14 TDIF13 TDIF12 TDIF11 TDIF10 TDIF9 TDIF8 TDIF7 TDIF6 TDIF5...
  • Page 316 ISD94100 Series Technical Reference Manual Description Bits PDMA Channel 10 Transfer Done Flag Register This bit indicates PDMA channel 10 transfer has been finished or not, user can write 1 to clear this bits. [10] TDIF10 0 = PDMA channel 10 transfer has not finished. 1 = PDMA channel 10 has finished transmission.
  • Page 317 ISD94100 Series Technical Reference Manual Description Bits This bit indicates PDMA channel 1 transfer has been finished or not, user can write 1 to clear this bits. 0 = PDMA channel 1 transfer has not finished. 1 = PDMA channel 1 has finished transmission. PDMA Channel 0 Transfer Done Flag Register This bit indicates PDMA channel 0 transfer has been finished or not, user can write 1 to clear this bits.
  • Page 318 ISD94100 Series Technical Reference Manual PDMA Transfer Alignment Status Register (PDMA_ALIGN) Offset R/W Description Reset Value Register PDMA_ALIGN PDMA_BA + 0x428 R/W PDMA Transfer Alignment Status Register 0x0000_0000 Reserved Reserved ALIGN15 ALIGN14 ALIGN13 ALIGN12 ALIGN11 ALIGN10 ALIGN9 ALIGN8 ALIGN7 ALIGN6 ALIGN5 ALIGN4 ALIGN3...
  • Page 319 ISD94100 Series Technical Reference Manual Description Bits 1 = PDMA channel 11 source address or destination address is not follow transfer width setting. Note: Software can write 1 to clear this bit. PDMA Channel 10 Transfer Alignment Flag Register 0 = PDMA channel 10 source address and destination address both follow transfer width setting.
  • Page 320 ISD94100 Series Technical Reference Manual Description Bits setting. Note: Software can write 1 to clear this bit. PDMA Channel 2 Transfer Alignment Flag Register 0 = PDMA channel 2 source address and destination address both follow transfer width setting. ALIGN2 1 = PDMA channel 2 source address or destination address is not follow transfer width setting.
  • Page 321 ISD94100 Series Technical Reference Manual PDMA Transfer Active Flag Register (PDMA_TACTSTS) Offset R/W Description Reset Value Register PDMA_TACTSTS PDMA_BA + 0x42C R PDMA Transfer Active Flag Register 0x0000_0000 Reserved Reserved TXACTF15 TXACTF14 TXACTF13 TXACTF12 TXACTF11 TXACTF10 TXACTF9 TXACTF8 TXACTF7 TXACTF6 TXACTF5 TXACTF4 TXACTF3...
  • Page 322 ISD94100 Series Technical Reference Manual Description Bits 1 = PDMA channel 8 is in active. PDMA Channel 7 Transfer on Active Flag Register (Read Only) TXACTF7 0 = PDMA channel 7 is not finished. 1 = PDMA channel 7 is in active. PDMA Channel 6 Transfer on Active Flag Register (Read Only) TXACTF6 0 = PDMA channel 6 is not finished.
  • Page 323 ISD94100 Series Technical Reference Manual PDMA Time-out Prescaler Register (PDMA_TOUTPSC) Offset R/W Description Reset Value Register PDMA_TOUTPSC PDMA_BA + 0x430 R/W PDMA Time-out Prescaler Register 0x0000_0000 Reserved Reserved Reserved Reserved TOUTPSC1 Reserved TOUTPSC0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:7] Reserved reset value.
  • Page 324 ISD94100 Series Technical Reference Manual PDMA Time-out Enable Register (PDMA_TOUTEN) Offset R/W Description Reset Value Register PDMA_TOUTEN PDMA_BA + 0x434 R/W PDMA Time-out Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved TOUTEN1 TOUTEN0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:2] Reserved reset value.
  • Page 325 ISD94100 Series Technical Reference Manual PDMA Time-out Interrupt Enable Register (PDMA_TOUTIEN) Offset R/W Description Reset Value Register PDMA_TOUTIEN PDMA_BA + 0x438 R/W PDMA Time-out Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved TOUTIEN1 TOUTIEN0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:2] Reserved reset value.
  • Page 326 ISD94100 Series Technical Reference Manual PDMA Scatter-gather Descriptor Table Base Address Register (PDMA_SCATBA) Offset R/W Description Reset Value Register PDMA Scatter-Gather Descriptor Table Base Address PDMA_SCATBA PDMA_BA + 0x43C R/W 0x2000_0000 Register SCATBA SCATBA Reserved Reserved Description Bits PDMA Scatter-gather Descriptor Table Address Register In Scatter-Gather mode, this is the base address for calculating the next link - list address.
  • Page 327 ISD94100 Series Technical Reference Manual PDMA Time-out Period Counter Register 0 (PDMA_TOC0_1) Offset R/W Description Reset Value Register PDMA_TOC0_1 PDMA_BA + 0x440 R/W PDMA Time-out Counter Ch1 and Ch0 Register 0xFFFF_FFFF TOC1 TOC1 TOC0 TOC0 Description Bits Time-out Counter for Channel 1 [31:16] TOC1 This controls the period of time-out function for channel 1.
  • Page 328 ISD94100 Series Technical Reference Manual PDMA Channel Reset Register (PDMA_CHRST) Offset R/W Description Reset Value Register PDMA_CHRST PDMA_BA + 0x460 R/W PDMA Channel Reset Register 0x0000_0000 Reserved Reserved CH15RST CH14RST CH13RST CH12RST CH11RST CH10RST CH9RST CH8RST CH7RST CH6RST CH5RST CH4RST CH3RST CH2RST CH1RST...
  • Page 329 ISD94100 Series Technical Reference Manual Description Bits Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL. Channel 10 Reset 0 = corresponding channel 10 not reset. [10] CH10RST 1 = corresponding channel 10 is reset. Note 1: This bit will be cleared automatically after finishing reset.
  • Page 330 ISD94100 Series Technical Reference Manual Description Bits 1 = corresponding channel 2 is reset. Note 1: This bit will be cleared automatically after finishing reset. Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL. Channel 1 Reset 0 = corresponding channel 1 not reset.
  • Page 331 ISD94100 Series Technical Reference Manual PDMA Request Source Select Register 0 (PDMA_REQSEL0_3) Offset R/W Description Reset Value Register PDMA_REQSEL0_3 PDMA_BA + 0x480 R/W PDMA Request Source Select Register 0 0x0000_0000 Reserved REQSRC3 Reserved REQSRC2 Reserved REQSRC1 Reserved REQSRC0 Description Bits Reserved.
  • Page 332 ISD94100 Series Technical Reference Manual Description Bits 5 = Channel connects to UART0_RX. 20 = Channel connects to SPI0_TX. 21 = Channel connects to SPI0_RX. 22 = Channel connects to SPI1_TX. 23 = Channel connects to SPI1_RX. 24 = Channel connects to SPI2_TX. 25 = Channel connects to SPI2_RX.
  • Page 333 ISD94100 Series Technical Reference Manual PDMA Request Source Select Register 1 (PDMA_REQSEL4_7) Offset R/W Description Reset Value Register PDMA_REQSEL4_7 PDMA_BA + 0x484 R/W PDMA Request Source Select Register 1 0x0000_0000 Reserved REQSRC7 Reserved REQSRC6 Reserved REQSRC5 Reserved REQSRC4 Description Bits Reserved.
  • Page 334 ISD94100 Series Technical Reference Manual PDMA Request Source Select Register 2 (PDMA_REQSEL8_11) Offset R/W Description Reset Value Register PDMA_REQSEL8_11 PDMA_BA + 0x488 R/W PDMA Request Source Select Register 2 0x0000_0000 Reserved REQSRC11 Reserved REQSRC10 Reserved REQSRC9 Reserved REQSRC8 Description Bits Reserved.
  • Page 335 ISD94100 Series Technical Reference Manual PDMA Request Source Select Register 3 (PDMA_REQSEL12_15) Offset R/W Description Reset Value Register PDMA_REQSEL12_15 PDMA_BA + 0x48C R/W PDMA Request Source Select Register 3 0x0000_0000 Reserved REQSRC15 Reserved REQSRC14 Reserved REQSRC13 Reserved REQSRC12 Description Bits Reserved.
  • Page 336 ISD94100 Series Technical Reference Manual PDMA Stride Transfer Count Register n (PDMA_STCRn) Offset R/W Description Reset Value Register PDMA_STCR0 PDMA_BA + 0x500 R/W Stride Transfer Count Register of PDMA Channel 0 0x0000_0000 PDMA_STCR1 PDMA_BA + 0x508 R/W Stride Transfer Count Register of PDMA Channel 1 0x0000_0000 PDMA_STCR2 PDMA_BA + 0x510...
  • Page 337 ISD94100 Series Technical Reference Manual PDMA Address Stride Offset Control Register n (PDMA_ASOCRn) Offset R/W Description Reset Value Register PDMA_ASOCR0 PDMA_BA + 0x504 R/W Address Stride Offset Register of PDMA Channel 0 0x0000_0000 PDMA_ASOCR1 PDMA_BA + 0x50C R/W Address Stride Offset Register of PDMA Channel 1 0x0000_0000 PDMA_ASOCR2 PDMA_BA + 0x514...

  • Page 338: Timer Controller (Tmr)

    ISD94100 Series Technical Reference Manual Timer Controller (TMR) 6.7.1 Overview The Timer controller contains four 32-bit multi-functional timers, Timer0, 1, 2 and 3. These timers can be used to count, or time external events that drive the Timer input pins. Or the four timers can be configured as four PWM generators;...
  • Page 339 ISD94100 Series Technical Reference Manual  PWM zero point, period, zero or period point, up-count compared or down-count compared point events Sep 9, 2019 Page 339 of 928 Rev1.09...

  • Page 340: Block Diagram

    ISD94100 Series Technical Reference Manual 6.7.3 Block Diagram Timer Controller block diagram is shown below. WKEN 24 - bit CMPDAT (TIMERx_CTL[23]) (TIMERx_CMP[23:0]) Timer RSTCNT(TIMERx_CTL[26] TWKF Wakeup Reset counter (TIMERx_INTSTS[1]) CNTEN(TIMERx_CTL[30] (TIMERx_INTSTS[0]) TMRx_CLK 8 - bit 24 - bit up counter Prescale TM0 ~ TM3 EXTCNTEN...

  • Page 341: Figure 6.7-2 Clock Source Of Timer Controller

    ISD94100 Series Technical Reference Manual TMR0SEL (CLK_CLKSEL1[10:8]) TMR1SEL (CLK_CLKSEL1[14:12]) TMR0CKEN (CLK_APBCLK0[2]) HIRC TMR1CKEN (CLK_APBCLK0[3]) LIRC TMR0_CLK TM0~TM1 TMR1_CLK PCLK0 TMR2SEL (CLK_CLKSEL1[18:16]) TMR3SEL (CLK_CLKSEL1[22:20]) HIRC TMR2CKEN (CLK_APBCLK0[4]) TMR3CKEN (CLK_APBCLK0[5]) LIRC TMR2_CLK TM2~TM3 TMR3_CLK PCLK1 Legend: HXT = High Speed External clock signal LXT = Low Speed External clock signal HIRC = High Speed Internal clock signal LIRC = Low Speed Internal clock signal...

  • Page 342: Figure 6.7-3 Pwm Generator Overview Block Diagram

    ISD94100 Series Technical Reference Manual NVIC TIMERx_PWM TMx, x=0~3 (PWMx_CH0) TMx_EXT, x=0~3 PCLK0/1 (PWMx_CH1) TMR0 TMR1 TMR2 TMR3 Figure 6.7-3 PWM Generator Overview Block Diagram In PWM mode, the timer clock source, i.e. now the PWM system clock, TMR0_CLK and TMR1_CLK clock sources are fixed to be from PCLK0;...

  • Page 343: Figure 6.7-5 Pwm Counter Clock Source Control

    ISD94100 Series Technical Reference Manual CLKSRC (TIMERx_PWMCLKSRC[2:0]) TMRx_CLK TMR0_INT TMRx_PWMCLK TMR1_INT TMR2_INT TMR3_INT Figure 6.7-5 PWM Counter Clock Source Control Figure 6.7-6 and Figure 6.7-7 illustrate the architecture of PWM independent mode and complementary mode. Both independent mode and complementary mode support PWMx_CH0 and PWMx_CH1 output channels in each PWM generator.

  • Page 344: Basic Configuration

    ISD94100 Series Technical Reference Manual Interrupt events Interrupt NVIC Generator Trigger events Trigger Generator (PWMx_CH0) Comparator TMRx_PWMCLK Pulse Output Prescale Counter Generator Control TMx_EXT (PWMx_CH1) Note: denotes interrupt events denotes trigger events denotes interrupt, trigger and pulse generate events Figure 6.7-7 PWM Complementary Mode Architecture Diagram 6.7.4 Basic Configuration Typically software needs to configure the registers below to configure a timer:...

  • Page 345: Timer Functional Description

    ISD94100 Series Technical Reference Manual PD.8 MFP2 PD.2 MFP5 PA.12 MFP2 TM0_EXT PD.9 MFP2 PA.14 MFP2 PD.4 MFP5 TM1_EXT PA.15 MFP2 6.7.4.2 TIMER23 basic configurations  Clock source configuration – Enable TIMER2 peripheral clock in TMR2CKEN (CLK_APBCLK0[4]). – Enable TIMER3 peripheral clock in TMR2CKEN (CLK_APBCLK0[5]). ...
  • Page 346 ISD94100 Series Technical Reference Manual continuous counting operation modes. Timer input clock or event source is divided by (PSC+1) before it is fed to the 24 bit up counter. By default the 8-bit prescaler PSC (TIMERx_CTL[7:0]) value is 0. 6.7.5.3 One–shot Mode Writing 0b00 into TIMERx_CTL[28:27] selects one-shot mode for that timer.

  • Page 347: Figure 6.7-8 Continuous Counting Mode

    ISD94100 Series Technical Reference Manual For example, if CMPDAT value is initially set as 80, when CNT reaches 80, timer raises TIF and generates interrupt (if interrupt enabled), and counting continues. Now assume software clears TIF and re-set CMPDAT value to 200, then when CNT reaches 200 timer will raise TIF and generate interrupt again.

  • Page 348: Figure 6.7-9 External Capture Mode

    ISD94100 Series Technical Reference Manual User can enable or disable TMx_EXT pin de-bounce circuit by setting CAPDBEN (TIMERx_EXTCTL[6]). The transition frequency of TMx_EXT pin should be less than 1/3 PCLK if TMx_EXT pin de-bounce disabled or less than 1/8 PCLK if TMx_EXT pin de-bounce enabled to assure the capture function can be work normally, and user can also select edge transition detection of TMx_EXT pin by setting CAPEDGE (TIMERx_EXTCTL[14:12]).

  • Page 349: Figure 6.7-11 Internal Timer Trigger

    ISD94100 Series Technical Reference Manual When the TRGPDMA (TIMERx_TRGCTL[4]) is set, if the timer interrupt signal is generated, the timer controller will trigger PDMA. TRGPWM(TIMERx_TRGCTL[1]) Trigger PWM time-out interrupt signal capture interrupt signal TRGSSEL (TIMERx_TRGCTL[0]) TRGADC(TIMERx_TRGCTL[2]) Trigger ADC time-out interrupt signal capture interrupt signal TRGSSEL (TIMERx_TRGCTL[0])

  • Page 350: Pwm Functional Description

    ISD94100 Series Technical Reference Manual transition of INTR_TMR_TRG. Then Timer0/2 counter mode function will be disabled and INTRGEN (TIMERx_CTL[19]) will be cleared by hardware then Timer1/3 will stop counting also. At the same time, the Timer1/3 CNT value will be saved into Timer1/3 CAPDAT (TIMERx_CAP[23:0]). User can use inter-timer trigger mode to measure the period of external event (TMx) more precisely.

  • Page 351: Figure 6.7-13 Pwm Prescale Waveform In Up Count Type

    ISD94100 Series Technical Reference Manual Figure 6.7-13 PWM Prescale Waveform in Up Count Type 6.7.6.2 PWM Counter PWM supports three counter types operation: up count, down count and up-down count types. 6.7.6.3 Up Count Type When PWM counter is set to up count type, CNTTYPE (TIMERx_PWMCTL[2:1]) is 0x0, it starts up-counting from zero to PERIOD (TIMERx_PWMPERIOD[15:0]).

  • Page 352: Figure 6.7-15 Pwm Down Count Type

    ISD94100 Series Technical Reference Manual PERIOD = 5 PERIOD = 8 PERIOD = 8 PWMCNT (TIMERx_PWMCNT[15:0]) PWM Period PWM Period PWM Period PWMCNTEN (TIMERx_PWMCTL[0]) zero point event period point event Figure 6.7-15 PWM Down Count Type 6.7.6.5 Up-Down Count Type When PWM counter is set to up-down count type, CNTTYPE (TIMERx_PWMCTL[2:1]) is 0x2, it starts counting up from zero to PERIOD and then starts counting down to zero.

  • Page 353: Figure 6.7-17 Pwm Comparator Events In Up-Down Count Type

    ISD94100 Series Technical Reference Manual 6.7.6.6 PWM Counter Operation mode The PWM counter supports two operation modes: one-shot mode and auto-reload mode. PWM counter will operate in one-shot mode if CNTMODE (TIMERx_PWMCTL[3]) bit is set to 1, and operate in auto-reload mode if CNTMODE bit is set to 0. In both modes, CMP (TIMERx_PWMCMPDAT[15:0]) and PERIOD (TIMERx_PWMPERIOD[15:0]) should be written first and then set CNTEN (TIMERx_PWMCTL[0]) bit to 1 to start counter running.

  • Page 354: Figure 6.7-18 Period Loading Mode With Up Count Type

    ISD94100 Series Technical Reference Manual PERIOD DATA1 denotes the first updated PERIOD data by user and so on, CMP also follows this rule. The following steps are the sequence of Figure 6.7-18. 1. User writes CMP DATA1 to CMP at point 1. 2.

  • Page 355: Figure 6.7-19 Immediately Loading Mode With Up Count Type

    ISD94100 Series Technical Reference Manual point 1 point 2 point 3 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPBUF CMPDAT DATA1 CNT wraparound 0x1FFFF PERIOD DATA1 PERIOD DATA0 CMPDAT DATA1 PERIOD DATA2 CMPDAT DATA0 0x10000...

  • Page 356: Figure 6.7-21 Pwm Pulse Generation In Up Count Type

    ISD94100 Series Technical Reference Manual PERIOD CMPDAT Zero PWM OUT Figure 6.7-21 PWM Pulse Generation in Up Count Type PERIOD CMPDAT Zero PWM OUT PWM period Figure 6.7-22 PWM Pulse Generation in Down Count Type The PWM generation events may sometimes generated at the same time, as the reason, events priority between different counter types should be take care are list in Table 6.7.6-1 , Table 6.7.6-2 and Table 6.7.6-3, event priority in up count type, event priority in down count type and event priority in up-down count type.

  • Page 357: Figure 6.7-23 Pwm 0% To 100% Duty Cycle In Up Count Type And Up-Down Count Type

    ISD94100 Series Technical Reference Manual Priority Period and CMPD point event PWM output (CMP = PERIOD) 1 (High) Compare down event High 2 (Low) Period event Table 6.7.6-2 PWM Pulse Generation Event Priority in Down Count Type Priority CMPU And CMPU Point Event PWM Output (CMP = PERIOD) 1 (High)

  • Page 358: Figure 6.7-24 Pwm Independent Mode Output Waveform

    ISD94100 Series Technical Reference Manual in Figure 6.7-24. PWMx_CH0 PWMx_CH1 Figure 6.7-24 PWM Independent Mode Output Waveform 6.7.6.13 Complementary mode When OUTMODE (TIMERx_PWMCTL[16]) bit is set to 1, PWM output operates in complementary mode. In this mode, both PWMx_CH0 and PWMx_CH1 can output waveform and PWMx_CH1 must always be the complement of PWMx_CH0 as shown in Figure 6.7-25.

  • Page 359: Figure 6.7-27 Pwmx_Ch0 And Pwmx_Ch1 Output Control In Complementary Mode

    ISD94100 Series Technical Reference Manual complementary control dead-time insertion control (PWMx_CH0) Independent Mode Dead-Time Pulse Three Steps 12-bits Generator TMx_EXT (PWMx_CH1) Independent Mode Dead-Time Three Steps 12-bits DTEN DTCNT (TIMERx_PWMDTCTL[16]) (TIMERx_PWMDTCTL[11:0]) DTCKSEL (TIMERx_PWMDTCTL[24]) Figure 6.7-27 PWMx_CH0 and PWMx_CH1 Output Control in Complementary Mode 6.7.6.15 Dead-Time Insertion Control In the complementary application, the complement channels may drive the external devices like power switches.

  • Page 360: Figure 6.7-29 Pwm Output Mask Control Waveform

    ISD94100 Series Technical Reference Manual 6.7.6.16 PWM Mask Output Control PWMx_CH0/CH1 output value can be masked to specified logic states by setting MSKEN0/1 (TIMERx_PWMMSKEN[1:0]) and MSKDAT0/1 (TIMERx_PWMMSK[1:0]). The PWM output mask function is useful when controlling various types of Electrically Commutated Motor (ECM) like a BLDC motor.

  • Page 361: Figure 6.7-30 Pwmx_Ch0 And Pwmx_Ch1 Polarity Control With Dead-Time Insertion

    ISD94100 Series Technical Reference Manual Initial State PWM Starts PWMx_CH0 PWMx_CH1 PWMx_CH0 (PINV0=0) PWMx_CH1 (PINV1=0) PWMx_CH0 (PINV0=1) PWMx_CH1 (PINV1=0) PWMx_CH0 (PINV0=0) PWMx_CH1 (PINV1=1) (PINV0=1) PWMx_CH0 (PINV1=1) PWMx_CH1 Note1: dead-time insertion Note2: PINV0/PIV1, it controls the output polar inverse Figure 6.7-30 PWMx_CH0 and PWMx_CH1 Polarity Control with Dead-Time Insertion 6.7.6.18 PWM Interrupt Generator There are independent interrupts for each PWM as shown in Figure 6.7-31.

  • Page 362: Figure 6.7-31 Pwm Interrupt Architecture Diagram

    ISD94100 Series Technical Reference Manual ZIF (TIMERx_PWMINTSTS0[0]) ZIEN (TIMERx_PWMINTEN0[0]) PIF (TIMERx_PWMINTSTS0[1]) PIEN (TIMERx_PWMINTEN0[1]) CMPUIF (TIMERx_PWMINTSTS0[2]) CMPUIEN (TIMERx_PWMINTEN0[2]) PWMx_INT/TMRx_INT CMPDIF (TIMERx_PWMINTSTS0[3]) CMPDIEN (TIMERx_PWMINTEN0[3]) Figure 6.7-31 PWM Interrupt Architecture Diagram 6.7.6.19 PWM Trigger ADC Generator PWM counter event can be one of the ADC conversion trigger source. User sets TRGSEL (TIMERx_PWMADCTS[3:0]) to select which PWM counter event can trigger ADC conversion after TRGEN (TIMERx_PWMADCTS [7]) is enabled.

  • Page 363: Register Map

    ISD94100 Series Technical Reference Manual 6.7.7 Register Map R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register TIMER Base Address: TMR01_BA = 0x4005_0000 TMR23_BA = 0x4005_1000 TIMER0_CTL TMR01_BA+0x00 R/W Timer0 Control Register 0x0000_0005 TIMER0_CMP TMR01_BA+0x04...
  • Page 364 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register TIMER Base Address: TMR01_BA = 0x4005_0000 TMR23_BA = 0x4005_1000 TIMER0_PWMSTRG TMR01_BA+0x98 Timer0 PWM Synchronous Trigger Register 0x0000_0000 TIMER0_PWMSTATUS TMR01_BA+0x9C R/W Timer0 PWM Status Register 0x0000_0000 TIMER0_PWMPBUF TMR01_BA+0xA0 Timer0 PWM Period Buffer Register 0x0000_0000 TIMER0_PWMCMPBUF TMR01_BA+0xA4 Timer0 PWM Comparator Buffer Register...
  • Page 365 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register TIMER Base Address: TMR01_BA = 0x4005_0000 TMR23_BA = 0x4005_1000 TIMER1_PWMADCTS TMR01_BA+0x190 R/W Timer1 PWM ADC Trigger Source Select Register 0x0000_0000 TIMER1_PWMSCTL TMR01_BA+0x194 R/W Timer1 PWM Synchronous Control Register 0x0000_0000 TIMER1_PWMSSTRG TMR01_BA+0x198 Timer1 PWM Synchronous Start Trigger Register...
  • Page 366 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register TIMER Base Address: TMR01_BA = 0x4005_0000 TMR23_BA = 0x4005_1000 TIMER2_PWMINTEN0 TMR23_BA+0x80 R/W Timer2 PWM Interrupt Enable Register 0 0x0000_0000 TIMER2_PWMINTSTS0 TMR23_BA+0x88 R/W Timer2 PWM Interrupt Status Register 0 0x0000_0000 TIMER2_PWMADCTS TMR23_BA+0x90 R/W Timer2 PWM ADC Trigger Source Select Register...
  • Page 367 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register TIMER Base Address: TMR01_BA = 0x4005_0000 TMR23_BA = 0x4005_1000 TIMER3_PWMPOLCTL TMR23_BA+0x174 R/W Timer3 PWM Pin Output Polar Control Register 0x0000_0000 TIMER3_PWMPOEN TMR23_BA+0x178 R/W Timer3 PWM Pin Output Enable Register 0x0000_0000 TIMER3_PWMINTEN0 TMR23_BA+0x180...

  • Page 368: Register Description

    ISD94100 Series Technical Reference Manual 6.7.8 Register Description Timer Control Register (TIMERx_CTL) Offset R/W Description Reset Value Register TIMER0_CTL TMR01_BA+0x00 R/W Timer0 Control Register 0x0000_0005 TIMER1_CTL TMR01_BA+0x100 R/W Timer1 Control Register 0x0000_0005 TIMER2_CTL TMR23_BA+0x00 R/W Timer2 Control Register 0x0000_0005 TIMER3_CTL TMR23_BA+0x100 R/W Timer3 Control Register 0x0000_0005...
  • Page 369 ISD94100 Series Technical Reference Manual 00 = The Timer controller is operated in One-shot mode. 01 = The Timer controller is operated in Periodic mode. 10 = The Timer controller is operated in Toggle-output mode. 11 = The Timer controller is operated in Continuous Counting mode. Reserved.
  • Page 370 ISD94100 Series Technical Reference Manual reset value. Prescale Counter Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up [7:0] counter. If this field is 0 (PSC = 0), then there is no scaling. Note: Overwriting prescale counter value will reset internal 8-bit prescale counter and 24- bit up counter value.
  • Page 371 ISD94100 Series Technical Reference Manual Timer Comparator Register (TIMERx_CMP) Offset R/W Description Reset Value Register TIMER0_CMP TMR01_BA+0x04 R/W Timer0 Comparator Register 0x0000_0000 TIMER1_CMP TMR01_BA+0x104 R/W Timer1 Comparator Register 0x0000_0000 TIMER2_CMP TMR23_BA+0x04 R/W Timer2 Comparator Register 0x0000_0000 TIMER3_CMP TMR23_BA+0x104 R/W Timer3 Comparator Register 0x0000_0000 Reserved CMPDAT...
  • Page 372 ISD94100 Series Technical Reference Manual Timer Interrupt Status Register (TIMERx_INTSTS) Offset R/W Description Reset Value Register TIMER0_INTSTS TMR01_BA+0x08 R/W Timer0 Interrupt Status Register 0x0000_0000 TIMER1_INTSTS TMR01_BA+0x108 R/W Timer1 Interrupt Status Register 0x0000_0000 TIMER2_INTSTS TMR23_BA+0x08 R/W Timer2 Interrupt Status Register 0x0000_0000 TIMER3_INTSTS TMR23_BA+0x108 R/W Timer3 Interrupt Status Register...
  • Page 373 ISD94100 Series Technical Reference Manual Timer Data Register (TIMERx_CNT) Offset R/W Description Reset Value Register TIMER0_CNT TMR01_BA+0x0C R/W Timer0 Data Register 0x0000_0000 TIMER1_CNT TMR01_BA+0x10C R/W Timer1 Data Register 0x0000_0000 TIMER2_CNT TMR23_BA+0x0C R/W Timer2 Data Register 0x0000_0000 TIMER3_CNT TMR23_BA+0x10C R/W Timer3 Data Register 0x0000_0000 RSTACT Reserved...
  • Page 374 ISD94100 Series Technical Reference Manual Timer Capture Data Register (TIMERx_CAP) Offset R/W Description Reset Value Register TIMER0_CAP TMR01_BA+0x10 Timer0 Capture Data Register 0x0000_0000 TIMER1_CAP TMR01_BA+0x110 Timer1 Capture Data Register 0x0000_0000 TIMER2_CAP TMR23_BA+0x10 Timer2 Capture Data Register 0x0000_0000 TIMER3_CAP TMR23_BA+0x110 Timer3 Capture Data Register 0x0000_0000 Reserved CAPDAT...
  • Page 375 ISD94100 Series Technical Reference Manual Timer External Control Register (TIMERx_EXTCTL) Offset R/W Description Reset Value Register TIMER0_EXTCTL TMR01_BA+0x14 R/W Timer0 External Control Register 0x0000_0000 TIMER1_EXTCTL TMR01_BA+0x114 R/W Timer1 External Control Register 0x0000_0000 TIMER2_EXTCTL TMR23_BA+0x14 R/W Timer2 External Control Register 0x0000_0000 TIMER3_EXTCTL TMR23_BA+0x114 R/W Timer3 External Control Register...
  • Page 376 ISD94100 Series Technical Reference Manual Timer Counter Pin De-bounce Enable Bit 0 = TMx (x= 0~3) pin de-bounce Disabled. CNTDBEN 1 = TMx (x= 0~3) pin de-bounce Enabled. Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. Timer External Capture Pin De-bounce Enable Bit 0 = TMx_EXT (x= 0~3) pin de-bounce Disabled.
  • Page 377 ISD94100 Series Technical Reference Manual Timer External Interrupt Status Register (TIMERx_EINTSTS) Offset R/W Description Reset Value Register TIMER0_EINTSTS TMR01_BA+0x18 R/W Timer0 External Interrupt Status Register 0x0000_0000 TIMER1_EINTSTS TMR01_BA+0x118 R/W Timer1 External Interrupt Status Register 0x0000_0000 TIMER2_EINTSTS TMR23_BA+0x18 R/W Timer2 External Interrupt Status Register 0x0000_0000 TIMER3_EINTSTS TMR23_BA+0x118...
  • Page 378 ISD94100 Series Technical Reference Manual Timer Trigger Control Register (TIMERx_TRGCTL) Offset R/W Description Reset Value Register TIMER0_TRGCTL TMR01_BA+0x1C R/W Timer0 Trigger Control Register 0x0000_0000 TIMER1_TRGCTL TMR01_BA+0x11C R/W Timer1 Trigger Control Register 0x0000_0000 TIMER2_TRGCTL TMR23_BA+0x1C R/W Timer2 Trigger Control Register 0x0000_0000 TIMER3_TRGCTL TMR23_BA+0x11C R/W Timer3 Trigger Control Register...
  • Page 379 ISD94100 Series Technical Reference Manual 0 = Timer interrupt trigger PWM Disabled. 1 = Timer interrupt trigger PWM Enabled. Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as PWM counter clock source. If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as PWM counter clock source.
  • Page 380 ISD94100 Series Technical Reference Manual Timer Alternative Control Register (TIMERx_ALTCTL) Offset R/W Description Reset Value Register TIMER0_ALTCTL TMR01_BA+0x20 R/W Timer0 Alternative Control Register 0x0000_0000 TIMER1_ALTCTL TMR01_BA+0x120 R/W Timer1 Alternative Control Register 0x0000_0000 TIMER2_ALTCTL TMR23_BA+0x20 R/W Timer2 Alternative Control Register 0x0000_0000 TIMER3_ALTCTL TMR23_BA+0x120 R/W Timer3 Alternative Control Register...
  • Page 381 ISD94100 Series Technical Reference Manual Timer PWM Control Register (TIMERx_PWMCTL) Offset R/W Description Reset Value Register TIMER0_PWMCTL TMR01_BA+0x40 R/W Timer0 PWM Control Register 0x0000_0000 TIMER1_PWMCTL TMR01_BA+0x140 R/W Timer1 PWM Control Register 0x0000_0000 TIMER2_PWMCTL TMR23_BA+0x40 R/W Timer2 PWM Control Register 0x0000_0000 TIMER3_PWMCTL TMR23_BA+0x140 R/W Timer3 PWM Control Register...
  • Page 382 ISD94100 Series Technical Reference Manual enabled/disabled. If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. 1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP.
  • Page 383 ISD94100 Series Technical Reference Manual Timer PWM Counter Clock Source Register (TIMERx PWMCLKSRC) Offset R/W Description Reset Value Register TIMER0_PWMCLKSRC TMR01_BA+0x44 R/W Timer0 PWM Counter Clock Source Register 0x0000_0000 TIMER1_PWMCLKSRC TMR01_BA+0x144 R/W Timer1 PWM Counter Clock Source Register 0x0000_0000 TIMER2_PWMCLKSRC TMR23_BA+0x44 R/W Timer2 PWM Counter Clock Source Register 0x0000_0000 TIMER3_PWMCLKSRC TMR23_BA+0x144...
  • Page 384 ISD94100 Series Technical Reference Manual Timer PWM Counter Clock Pre-scale Register (TIMERx PWMCLKPSC) Offset R/W Description Reset Value Register TIMER0_PWMCLKPSC TMR01_BA+0x48 R/W Timer0 PWM Counter Clock Pre-scale Register 0x0000_0000 TIMER1_PWMCLKPSC TMR01_BA+0x148 R/W Timer1 PWM Counter Clock Pre-scale Register 0x0000_0000 TIMER2_PWMCLKPSC TMR23_BA+0x48 R/W Timer2 PWM Counter Clock Pre-scale Register 0x0000_0000 TIMER3_PWMCLKPSC TMR23_BA+0x148...
  • Page 385 ISD94100 Series Technical Reference Manual Timer PWM Clear Counter Register (TIMERx PWMCNTCLR) Offset R/W Description Reset Value Register TIMER0_PWMCNTCLR TMR01_BA+0x4C R/W Timer0 PWM Clear Counter Register 0x0000_0000 TIMER1_PWMCNTCLR TMR01_BA+0x14C R/W Timer1 PWM Clear Counter Register 0x0000_0000 TIMER2_PWMCNTCLR TMR23_BA+0x4C R/W Timer2 PWM Clear Counter Register 0x0000_0000 TIMER3_PWMCNTCLR TMR23_BA+0x14C R/W Timer3 PWM Clear Counter Register...
  • Page 386 ISD94100 Series Technical Reference Manual Timer PWM Period Register (TIMERx PWMPERIOD) Offset R/W Description Reset Value Register TIMER0_PWMPERIOD TMR01_BA+0x50 R/W Timer0 PWM Period Register 0x0000_0000 TIMER1_PWMPERIOD TMR01_BA+0x150 R/W Timer1 PWM Period Register 0x0000_0000 TIMER2_PWMPERIOD TMR23_BA+0x50 R/W Timer2 PWM Period Register 0x0000_0000 TIMER3_PWMPERIOD TMR23_BA+0x150...
  • Page 387 ISD94100 Series Technical Reference Manual Timer PWM Comparator Register (TIMERx PWMCMPDAT) Offset R/W Description Reset Value Register TIMER0_PWMCMPDAT TMR01_BA+0x54 R/W Timer0 PWM Comparator Register 0x0000_0000 TIMER1_PWMCMPDAT TMR01_BA+0x154 R/W Timer1 PWM Comparator Register 0x0000_0000 TIMER2_PWMCMPDAT TMR23_BA+0x54 R/W Timer2 PWM Comparator Register 0x0000_0000 TIMER3_PWMCMPDAT TMR23_BA+0x154 R/W Timer3 PWM Comparator Register...
  • Page 388 ISD94100 Series Technical Reference Manual Timer PWM Dead-Time Control Register (TIMERx PWMDTCTL) Offset R/W Description Reset Value Register TIMER0_PWMDTCTL TMR01_BA+0x58 R/W Timer0 PWM Dead-Time Control Register 0x0000_0000 TIMER1_PWMDTCTL TMR01_BA+0x158 R/W Timer1 PWM Dead-Time Control Register 0x0000_0000 TIMER2_PWMDTCTL TMR23_BA+0x58 R/W Timer2 PWM Dead-Time Control Register 0x0000_0000 TIMER3_PWMDTCTL TMR23_BA+0x158...
  • Page 389 ISD94100 Series Technical Reference Manual Timer PWM Counter Register (TIMERx PWMCNT) Offset R/W Description Reset Value Register TIMER0_PWMCNT TMR01_BA+0x5C Timer0 PWM Counter Register 0x0000_0000 TIMER1_PWMCNT TMR01_BA+0x15C Timer1 PWM Counter Register 0x0000_0000 TIMER2_PWMCNT TMR23_BA+0x5C Timer2 PWM Counter Register 0x0000_0000 TIMER3_PWMCNT TMR23_BA+0x15C Timer3 PWM Counter Register 0x0000_0000 Reserved...
  • Page 390 ISD94100 Series Technical Reference Manual Timer PWM Output Mask Enable Register (TIMERx PWMMSKEN) Offset R/W Description Reset Value Register TIMER0_PWMMSKEN TMR01_BA+0x60 R/W Timer0 PWM Output Mask Enable Register 0x0000_0000 TIMER1_PWMMSKEN TMR01_BA+0x160 R/W Timer1 PWM Output Mask Enable Register 0x0000_0000 TIMER2_PWMMSKEN TMR23_BA+0x60 R/W Timer2 PWM Output Mask Enable Register 0x0000_0000...
  • Page 391 ISD94100 Series Technical Reference Manual Timer PWM Output Mask Data Control Register (TIMERx PWMMSK) Offset R/W Description Reset Value Register TIMER0_PWMMSK TMR01_BA+0x64 R/W Timer0 PWM Output Mask Data Control Register 0x0000_0000 TIMER1_PWMMSK TMR01_BA+0x164 R/W Timer1 PWM Output Mask Data Control Register 0x0000_0000 TIMER2_PWMMSK TMR23_BA+0x64...
  • Page 392 ISD94100 Series Technical Reference Manual Timer PWM Pin Output Polar Control Register (TIMERx PWMPOLCTL) Offset R/W Description Reset Value Register TIMER0_PWMPOLCTL TMR01_BA+0x74 R/W Timer0 PWM Pin Output Polar Control Register 0x0000_0000 TIMER1_PWMPOLCTL TMR01_BA+0x174 R/W Timer1 PWM Pin Output Polar Control Register 0x0000_0000 TIMER2_PWMPOLCTL TMR23_BA+0x74 R/W Timer2 PWM Pin Output Polar Control Register...
  • Page 393 ISD94100 Series Technical Reference Manual Timer PWM Pin Output Enable Register (TIMERx PWMPOEN) Offset R/W Description Reset Value Register TIMER0_PWMPOEN TMR01_BA+0x78 R/W Timer0 PWM Pin Output Enable Register 0x0000_0000 TIMER1_PWMPOEN TMR01_BA+0x178 R/W Timer1 PWM Pin Output Enable Register 0x0000_0000 TIMER2_PWMPOEN TMR23_BA+0x78 R/W Timer2 PWM Pin Output Enable Register 0x0000_0000...
  • Page 394 ISD94100 Series Technical Reference Manual Timer PWM Interrupt Enable Register 0 (TIMERx PWMINTEN0) Offset R/W Description Reset Value Register TIMER0_PWMINTEN0 TMR01_BA+0x80 R/W Timer0 PWM Interrupt Enable Register 0 0x0000_0000 TIMER1_PWMINTEN0 TMR01_BA+0x180 R/W Timer1 PWM Interrupt Enable Register 0 0x0000_0000 TIMER2_PWMINTEN0 TMR23_BA+0x80 R/W Timer2 PWM Interrupt Enable Register 0 0x0000_0000...
  • Page 395 ISD94100 Series Technical Reference Manual Timer PWM Interrupt Status Register 0 (TIMERx PWMINTSTS0) Offset R/W Description Reset Value Register TIMER0_PWMINTSTS0 TMR01_BA+0x88 R/W Timer0 PWM Interrupt Status Register 0 0x0000_0000 TIMER1_PWMINTSTS0 TMR01_BA+0x188 R/W Timer1 PWM Interrupt Status Register 0 0x0000_0000 TIMER2_PWMINTSTS0 TMR23_BA+0x88 R/W Timer2 PWM Interrupt Status Register 0 0x0000_0000 TIMER3_PWMINTSTS0 TMR23_BA+0x188...
  • Page 396 ISD94100 Series Technical Reference Manual Timer PWM ADC Trigger Control Register (TIMERx PWMADCTS) Offset R/W Description Reset Value Register TIMER0_PWMADCTS TMR01_BA+0x90 R/W Timer0 PWM ADC Trigger Source Select Register 0x0000_0000 TIMER1_PWMADCTS TMR01_BA+0x190 R/W Timer1 PWM ADC Trigger Source Select Register 0x0000_0000 TIMER2_PWMADCTS TMR23_BA+0x90...
  • Page 397 ISD94100 Series Technical Reference Manual Timer PWM Synchronous Control Register (TIMERx PWMSCTL) Offset R/W Description Reset Value Register TIMER0_PWMSCTL TMR01_BA+0x94 R/W Timer0 PWM Synchronous Control Register 0x0000_0000 TIMER1_PWMSCTL TMR01_BA+0x194 R/W Timer1 PWM Synchronous Control Register 0x0000_0000 TIMER2_PWMSCTL TMR23_BA+0x94 R/W Timer2 PWM Synchronous Control Register 0x0000_0000 TIMER3_PWMSCTL TMR23_BA+0x194...
  • Page 398 ISD94100 Series Technical Reference Manual Timer PWM Synchronous Trigger Register (TIMERx PWMSTRG) Offset R/W Description Reset Value Register TIMER0_PWMSTRG TMR01_BA+0x98 Timer0 PWM Synchronous Trigger Register 0x0000_0000 TIMER2_PWMSTRG TMR23_BA+0x98 Timer2 PWM Synchronous Trigger Register 0x0000_0000 Reserved Reserved Reserved Reserved STRGEN Description Bits Reserved.
  • Page 399 ISD94100 Series Technical Reference Manual Timer PWM Status Register (TIMERx PWMSTATUS) Offset R/W Description Reset Value Register TIMER0_PWMSTATUS TMR01_BA+0x9C R/W Timer0 PWM Status Register 0x0000_0000 TIMER1_PWMSTATUS TMR01_BA+0x19C R/W Timer1 PWM Status Register 0x0000_0000 TIMER2_PWMSTATUS TMR23_BA+0x9C R/W Timer2 PWM Status Register 0x0000_0000 TIMER3_PWMSTATUS TMR23_BA+0x19C R/W Timer3 PWM Status Register...
  • Page 400 ISD94100 Series Technical Reference Manual Timer PWM Period Buffer Register (TIMERx PWMPBUF) Offset R/W Description Reset Value Register TIMER0_PWMPBUF TMR01_BA+0xA0 Timer0 PWM Period Buffer Register 0x0000_0000 TIMER1_PWMPBUF TMR01_BA+0x1A0 Timer1 PWM Period Buffer Register 0x0000_0000 TIMER2_PWMPBUF TMR23_BA+0xA0 Timer2 PWM Period Buffer Register 0x0000_0000 TIMER3_PWMPBUF TMR23_BA+0x1A0...
  • Page 401 ISD94100 Series Technical Reference Manual Timer PWM Comparator Buffer Register (TIMERx PWMCMPBUF) Offset R/W Description Reset Value Register TIMER0_PWMCMPBUF TMR01_BA+0xA4 Timer0 PWM Comparator Buffer Register 0x0000_0000 TIMER1_PWMCMPBUF TMR01_BA+0x1A4 Timer1 PWM Comparator Buffer Register 0x0000_0000 TIMER2_PWMCMPBUF TMR23_BA+0xA4 Timer2 PWM Comparator Buffer Register 0x0000_0000 TIMER3_PWMCMPBUF TMR23_BA+0x1A4 Timer3 PWM Comparator Buffer Register...

  • Page 402: Pwm Generator And Capture Timer (Pwm)

    ISD94100 Series Technical Reference Manual 6.8 PWM Generator and Capture Timer (PWM) 6.8.1 Overview The ISD94100 series provides one PWM generators － PWM0. It supports 6 channels of PWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit PWM counter with 16-bit comparator.
  • Page 403 ISD94100 Series Technical Reference Manual  Level detect brake source to auto recover function after brake condition removed  Supports interrupt on the following events:  PWM counter match zero, period value or compared value  Brake condition happened  Supports trigger EADC on the following events: ...

  • Page 404: Block Diagram

    ISD94100 Series Technical Reference Manual 6.8.3 Block Diagram PWM0_SYNC_OUT PWM0_SYNC_IN PWM0_BRAKE0 SYNC_IN NVIC_MUX SYNC_OUT PWM0_CH0 PWM0_BRAKE1 PWM0 CLOCK PWM0_CH5 CONTROLLER TIMER0 PDMA TIMER1 TIMER2 TIMER3 Clock Fail Brown-Out Detect SRAM Parity Error EADC CPU Lockup Brake Source Note: Only capture mode output to PDMA Figure 6.8-1 PWM Generator Overview Block Diagram PWM system clock frequency can be set equal or double to HCLK frequency as the Figure 6.8-2, the...

  • Page 405: Figure 6.8-3 Pwm Clock Source Control

    ISD94100 Series Technical Reference Manual Frequency Ratio HCLK PCLK HCLKSEL HCLKDIV APBnDIV PWMnSEL PCLK:PWM Clock Clock CLK_CLKSEL0[2:0] CLK_CLKDIV0[3: (CLK_CLKDIVn (CLK_CLKSEL2[N [2+4n:4n]), N Denotes 0 Or N Denotes 0 Or 1 HCLK PCLK PCLK Don’t care Don’t care Don’t care PLL/ 2 PLL/ 2 PLL/ 2 Table 6.8.3-1 PWM System Clock Source Control Registers Setting Table ECLKSRC0 (PWM0_CLKSRC[2:0])

  • Page 406: Figure 6.8-4 Pwm Independent Mode Architecture Diagram

    ISD94100 Series Technical Reference Manual PWM0_BRAKE0 Interrupt Interrupt events IRQ_MUX Generator Trigger events Trigger EADC Generator PWM0_BRAKE1 PWM0_CLK0 Prescaler0 Counter0 PWM0_CH0 Pulse Output 12bits 16bits Generator0 Control0 Comparator0 PWM0_BRAKE0 16bits PWM0_BRAKE1 Counter1 PWM0_CH1 Pulse Output 16bits Generator1 Control1 Comparator1 PWM0_BRAKE0 16bits PWM0_BRAKE1 PWM0_CLK2...

  • Page 407: Basic Configuration

    ISD94100 Series Technical Reference Manual PWM0_BRAKE0 Interrupt Events Interrupt IRQ_MUX Generator PWM0_BRAKE1 Trigger Events Trigger EADC/DAC Generator Free Trigger Comparator0 PWM0_SYNC_IN PWM0_CH0 Comparator0 PWM0_CLK0 Prescaler0 Pulse Output Counter0 12bits Generator0 Control0 PWM0_CH1 Comparator1 PWM0_BRAKE0 Free Trigger PWM0_BRAKE1 Comparator2 PWM0_CH2 Comparator2 PWM0_CLK2 Pulse Output...

  • Page 408: Functional Description

    ISD94100 Series Technical Reference Manual PB.1 MFP3 PWM0_CH1 PB.3 MFP1 PB.5 MFP2 PB.2 MFP3 PWM0_CH2 PB.6 MFP2 PC.4 MFP1 PB.3 MFP5 PB.7 MFP2 PWM0_CH3 PC.13 MFP1 PD.12 MFP3 PB.4 MFP5 PWM0_CH4 PB.8 MFP2 PC.14 MFP1 PB.9 MFP2 PWM0_CH5 PD.7 MFP1 PWM0_SYNC_IN PB.0 MFP1...

  • Page 409: Figure 6.8-7 Pwm0 Counter Waveform When Set Clear Counter

    ISD94100 Series Technical Reference Manual 6.8.5.2 PWM Counter PWM supports 3 counter types operation: Up Counter, Down Counter and Up-Down Counter types. For PWM channel0, CNT(PWM_CNT0[15:0]) can clear to 0x00 by CNTCLR0 (PWM_CNTCLR[0]). CNT will be cleared when prescale counter to 0, and CNTCLR will be set 0 by hardware automatically.

  • Page 410: Figure 6.8-9 Pwm Down Counter Type

    ISD94100 Series Technical Reference Manual 6.8.5.4 Down Counter Type When PWM counter is set to down counter type, CNTTYPEn (PWM_CTL1[2n+1:2n], n = 0,1..5) is 0x1, it starts down-counting from PERIOD to zero to complete a PWM period. The current counter value can be read from CNT (PWM_CNTn[15:0]) bits.

  • Page 411: Figure 6.8-10 Pwm Up-Down Counter Type

    ISD94100 Series Technical Reference Manual PERIOD = 4 PERIOD = 7 (PWM_CNTn[15:0]) DIRF (PWM_CNTn[16]) PWM Period PWM Period CNTENn (PWM_CNTEN[n]) zero point event center point event Note1: When in up-down count type, period interrupt flag occurs at center point event. Note2: n denotes channel 0,1..5 Figure 6.8-10 PWM Up-Down Counter Type 6.8.5.6...

  • Page 412: Figure 6.8-11 Pwm Compared Point Events In Up-Down Counter Type

    ISD94100 Series Technical Reference Manual PERIOD = 4 PERIOD = 7 PERIOD = 5 CMPDAT = 4 CMPDAT = 5 CMPDAT= 0 (PWM_CNTn[15:0]) DIRF (PWM_CNTn[16]) PWM Period PWM Period Up-count compared point event (CMPU) Down-count compared point event (CMPD) Note1: No CMPU event occurred when CMPDAT equals to PERIOD. Note2: n denotes channel 0,1..5 Figure 6.8-11 PWM Compared point Events in Up-Down Counter Type FTCMPDAT is a free trigger comparator register.

  • Page 413: Figure 6.8-12 Pwm Double Buffering Illustration

    ISD94100 Series Technical Reference Manual Load from PERIOD to PBUF, from FTCMPDAT to FTCMPBUF Initialize Load from CMPDAT start S/W Write CMPDAT S/W Write PERIOD to CMPBUF PERIOD PBUF CMPDAT CMPBUF FTCMPDAT FTCMPBUF S/W Write FTCMPDAT CMPU CMPD FTCMPU FTCMPD Figure 6.8-12 PWM Double Buffering Illustration 6.8.5.8 Period Loading Mode...

  • Page 414: Figure 6.8-13 Period Loading In Up-Count Mode

    ISD94100 Series Technical Reference Manual point 1 point 2 point 3 point 4 point 5 point 6 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPDAT DATA1 CMPBUF PERIOD DATA1 PERIOD DATA0 PERIOD DATA2 CMPDAT DATA1 CMPDAT DATA0...

  • Page 415: Figure 6.8-14 Immediately Loading In Up-Count Mode

    ISD94100 Series Technical Reference Manual point 1 point 2 point 3 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPBUF CMPDAT DATA1 CNT wraparound 0xFFFF PERIOD DATA1 PERIOD DATA0 CMPDAT DATA1 PERIOD DATA2 CMPDAT DATA0 CMPU...

  • Page 416: Figure 6.8-15 Window Loading In Up-Count Mode

    ISD94100 Series Technical Reference Manual point 3 point 7 point 1 point 2 point 4 point 5 point 6 point 8 point 9 CLKPSC DATA0 CLKPSC DATA3 CLKPSC CLKPSC DATA1 CLKPSC DATA2 CLKPSCBUF CLKPSC DATA0 CLKPSC DATA1 CLKPSC DATA2 CLKPSC DATA3 PERIOD PERIOD DATA0 PERIOD DATA 3...

  • Page 417: Figure 6.8-16 Center Loading In Up-Down-Count Mode

    ISD94100 Series Technical Reference Manual point 1 point 2 point 3 point 4 point 5 point 6 point 7 point 8 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPDAT DATA2 CMPBUF CMPDAT DATA0 CMPDAT DATA1...

  • Page 418: Figure 6.8-17 Pwm One-Shot Mode Output Waveform

    ISD94100 Series Technical Reference Manual point 1 point 2 point 3 point 4 point 5 point 6 PERIOD DATA1 Continuous one- One-shot shot PERIOD DATA0 CMPDAT DATA3 CMPDAT DATA0 PWM OUT Note: Write Load Figure 6.8-17 PWM One-shot Mode Output Waveform In Auto-reload mode, CMPDAT and PERIOD registers should be written first and then the CNTENn(PWM_CNTEN[n]) bit is set to 1 to enable PWM prescaler and start to run counter.

  • Page 419: Figure 6.8-18 Pwm Pulse Generation

    ISD94100 Series Technical Reference Manual Center Center CMPDATm CMPDATm CMPDATn CMPDATn Zero Zero PWM OUT PWM OUT PWM period PWM period Note: 1. Zero = L Note: 1. Zero = H 2. CMPUn = X 2. CMPUn = T 3. CMPUm = H 3.

  • Page 420: Table 6.8.5-2 Pwm Pulse Generation Event Priority For Down-Counter

    ISD94100 Series Technical Reference Manual Priority Down Event 1 (Highest) Zero event (CNT = zero) Compare down event of odd channel (CNT = CMPDm ) Compare down event of even channel (CNT = CMPDn ) 4 (Lowest) Period event (CNT = PERIOD) Table 6.8.5-2 PWM Pulse Generation Event Priority for Down-Counter Priority Up Event...

  • Page 421: Figure 6.8-20 Pwm Independent Mode Waveform

    ISD94100 Series Technical Reference Manual Setting: OUTMODE0 (PWM_CTL1[24]) = 0x0 PWM_CH0 PWM_CH1 Setting: OUTMODE2 (PWM_CTL1[25]) = 0x0 PWM_CH2 PWM_CH3 Setting: OUTMODE4 (PWM_CTL1[26]) = 0x0 PWM_CH4 PWM_CH5 Figure 6.8-20 PWM Independent Mode Waveform 6.8.5.16 Complementary mode Complementary mode is enabled when the pair channel corresponding PWMMODEn (PWM_CTL1[26:24]) bit set to 1.

  • Page 422: Figure 6.8-22 Pwm Group Function Waveform

    ISD94100 Series Technical Reference Manual function makes any channel of PWM0 in phase, user can control phase value and direction. 6.8.5.18 Group function Group function is enabled when GROUPEN (PWM_CTL0[24]) is set to 1, no matter in independent or complementary mode. This control allows all even PWM channels output to be controllable by PWM_PERIOD0 and PWM_CMPDAT0 registers and all odd PWM channels output to be controllable by PWM_PERIOD1 and PWM_CMPDAT1 registers.

  • Page 423: Figure 6.8-23 Pwm Sync_In Noise Filter Block Diagram

    ISD94100 Series Technical Reference Manual SFLTCSEL (PWM_SYNC[19:17]) HCLK SFLTCNT HCLK/2 SINPINV (PWM_SYNC[22:20]) HCLK/4 (PWM_SYNC[23]) HCLK/8 Sampling Clock HCLK/16 SYNC_IN HCLK/32 Noise filter HCLK/64 counter 3-bits HCLK/128 PWM0_SYNC_IN SNFLTEN (PWM_SYNC[16]) Figure 6.8-23 PWM SYNC_IN Noise Filter Block Diagram User can use SINSRCn (PWM_SYNC[13:8]) bits to select the synchronize source. When SINSRCn bits is set to 0, user can generate SYNC_IN signal for the next counter’s synchronization when PWM0_SYNC_IN pin is high or setting SWSYNCn (PWM_SWSYNC[2:0]) to 1.

  • Page 424: Figure 6.8-24 Pwm Counter Synchronous Function Block Diagram

    ISD94100 Series Technical Reference Manual SYNC_IN PHSENn SWSYNCn (PWM_SYNC[2:0]) (PWM_PHSn[15:0]) (PWM_SWSYNC[2:0]) PHSDIRn (PWM_SYNC[26:24]) PHS load signal CNT = 0 SYNC_OUT CNT = CMPDATm DIRF Disabled (PWM_CNTn[16]) 16-bits PWM SINSRCn 3 types counter (PWM_CNTn[15:0]) (PWM_SYNC[13:8]) Note: n denotes channel 0, 2, 4 Figure 6.8-24 WM Counter Synchronous Function Block Diagram Figure 6.8-25 is an example of the synchronous function in the up-down counter type.

  • Page 425: Figure 6.8-25 Pwm Synchronous Function With Synchronize Source From Sync_In Signal

    ISD94100 Series Technical Reference Manual CH0_PERIOD = 900 CH0_PERIOD = 600 PHSDIR0 = 1 (PWM_SYNC[24]) PHS = 0 (PWM_PHS0) PWM SYNC input PWM_CH0 PWM period PWM period PWM period CH2_PERIOD = 900 CH2_CMPDAT = 600 PHSDIR2 = 0 (PWM_SYNC[25]) PHS = 600 (PWM_PHS2) PWM_CH2 PWM period...

  • Page 426: Figure 6.8-27 Pwm0_Ch0 And Pwm0_Ch1 Output Control In Complementary Mode

    ISD94100 Series Technical Reference Manual Complementary Mode Dead Time Insertion Control PWM0_CH0 Pulse Dead Time Independent Mode Generation 12-bits Four Steps PWM0_CH1 Dead Time Independent Mode 12-bits Four Steps DTEN (PWM_DTCTL0_1[16]) DTCNT (PWM_DTCTL0_1[11:0]) Figure 6.8-27 PWM0_CH0 and PWM0_CH1 Output Control in Complementary Mode 6.8.5.21 Dead-Time Insertion In the complementary application, the complement channels may drive the external devices like power switches.

  • Page 427: Figure 6.8-28 Dead-Time Insertion

    ISD94100 Series Technical Reference Manual PWM_CH0 without Dead-Time PWM_CH1 without Dead-Time PWM_CH0 with Dead-Time PWM_CH1 with Dead-Time Dead-Time Interval Effect of Dead-Time for complementary pairs Figure 6.8-28 Dead-Time Insertion 6.8.5.22 PWM Mask Output Function Each of the PWM channel output value can be manually overridden with the settings in the PWM Mask Enable Control Register (PWM_MSKEN) and the PWM Masked Data Register (PWM_MSK) With these settings, the PWM channel outputs can be assigned to specified logic states independent of the duty cycle comparison units.

  • Page 428: Figure 6.8-30 Brake Noise Filter Block Diagram

    ISD94100 Series Technical Reference Manual many sampling clock cycles a filter will recognize the effective edge of the brake signal. In addition, it can be inversed by setting the BRKxPINV (x denotes input external pin 0 or 1) bits of PWM_BNF register to realize the polarity setup for the brake control signals.

  • Page 429: Figure 6.8-31 Brake Block Diagram For Pwm0_Ch0 And Pwm0_Ch1 Pair

    ISD94100 Series Technical Reference Manual BRKEIF0 or BRKEIF1 (PWM_INTSTS1[1:0]) Edge Detect Edge Detect Brake Interrupt Brake Source BRKEIEN0_1 (PWM_INTEN1[0]) BRK_INT BRKLIF0 or BRKLIF1 (PWM_INTSTS1[9:8]) Level Detect Brake Interrupt BRKLIEN0_1 (PWM_INTEN1[8]) BRKLSTS0 (PWM_INTSTS1[24]) BRKAEVEN BRKESTS0 (PWM_BRKCTL0[17:16]) (PWM_INTSTS1[16]) PWM_OUT0 Level Detect Low level Brake Source detection PWM_OUT1...

  • Page 430: Figure 6.8-32 Edge Detector Waveform For Pwm0_Ch0 And Pwm0_Ch1 Pair

    ISD94100 Series Technical Reference Manual Setting: BRKAEVEN = 3 (High) BRKAODD = 2 (Low) Edge Detect Brake Source BRKEIF0 s/w clear BRKEIF1 s/w clear BRKESTS0 BRKESTS1 PWM_CH0 PWM_CH1 PWM_CH0 signals resume at next start PWM_CH1 signals resume at next start of PWM period after BRKEIF0 clear of PWM period after BRKEIF1 clear Note:...

  • Page 431: Figure 6.8-34 Brake Source Block Diagram

    ISD94100 Series Technical Reference Manual shown in Figure 6.8-34. Among the above described brake sources, the brake source coming from system fail can still be specified to several different system fail conditions. These conditions include clock fail, Brown-out detect, SRAM parity check error and Core lockup. Figure 6.8-35 shows that by setting corresponding enable bits, the enabled system fail condition can be one of the sources to issue the Brake system fail to the PWM brake.

  • Page 432: Figure 6.8-36 Initial State And Polarity Control With Rising Edge Dead-Time Insertion

    ISD94100 Series Technical Reference Manual Initial State PWM Starts PWM_WGCTL0 PWM_WGCTL1 PWM_CH0 (PINV0=0) PWM_CH1 (PINV1=0) PWM_CH0 (PINV0=1) PWM_CH1 (PINV1=0) PWM_CH0 (PINV0=0) PWM_CH1 (PINV1=1) (PINV0=1) PWM_CH0 (PINV1=1) PWM_CH1 Dead-time insertion; It is only effective in complementary mode Note: PINVx: Negative Polarity control bits; It controls the PWM output initial state and polarity, x denotes 0 or 1.

  • Page 433: Figure 6.8-37 Pwm0_Ch0 And Pwm0_Ch1 Pair Interrupt Architecture Diagram

    ISD94100 Series Technical Reference Manual ZIF0 (PWM_INTSTS0[0]) ZIEN0 (PWM_INTEN0[0]) PIF0 (PWM_INTSTS0[8]) PIEN0 (PWM_INTEN0[8]) CMPUIF0 (PWM_INTSTS0[16]) CMPUIEN0 (PWM_INTEN0[16]) CMPDIF0 (PWM_INTSTS0[24]) CMPDIEN0 (PWM_INTEN0[24]) PWM_INT ZIF1 (PWM_INTSTS0[1]) ZIEN1 (PWM_INTEN0[1]) PIF1 (PWM_INTSTS0[9]) PIEN1 (PWM_INTEN0[9]) CMPUIF1 (PWM_INTSTS0[17]) CMPUIEN1 (PWM_INTEN0[17]) CMPDIF1 (PWM_INTSTS0[25]) CMPDIEN1 (PWM_INTEN0[25]) BRKEIF0 (PWM_INISTS1[0]) BRKEIF1 (PWM_INTSTS1[1]) BRKEIEN0_1 (PWM_INTEN1[0]) BRK_INT...

  • Page 434: Figure 6.8-38 Pwm0_Ch0 And Pwm0_Ch1 Pair Trigger Eadc Block Diagram

    ISD94100 Series Technical Reference Manual PWM_CH0 zero point PWM_CH0 period point PWM_CH0 period or zero point PWM_CH0 up-count compared point PWM_CH0 down-count compared point PWM_CH1 zero point PWM Trigger 0/ PWM_CH1 period point PWM Trigger 1 PWM_CH1 period or zero point EADC PWM_CH1 up-count compared point PWM_CH1 down-count compared point...

  • Page 435: Figure 6.8-40 Pwm0_Ch0 Capture Block Diagram

    ISD94100 Series Technical Reference Manual if the input channel has a rising transition or a falling transition, respectively. The capture function will also generate an interrupt CAP_INT (using PWM_INT vector) if the rising or falling latch occurs and the corresponding channel n’s rising or falling interrupt enable bits are set, where the CAPRIENn (PWM_CAPIEN[5:0]) rising...

  • Page 436: Figure 6.8-41 Capture Operation Waveform

    ISD94100 Series Technical Reference Manual the rising edge at channel n is detected, the corresponding CRLIFn (PWM_CAPIF[5:0]) bit is set by hardware. Similarly, a falling edge detection at channel n causes the corresponding CFLIFn (PWM_CAPIF[13:8]) bit is set by hardware. CRLIFn and CFLIFn bits can be cleared by software by writing ‘1’.
  • Page 437 ISD94100 Series Technical Reference Manual PWM_FCAPDATn) PWM counter time, where one PWM counter time is (CLKPSC+1) * PWM0_CLK clock time. In Figure 6.8-41, the high pulse width is 8+1-7 = 2 PWM counter time. 6.8.5.28 Capture PDMA Function The PWM module supports the PDMA transfer function when operating in the capture mode. When the corresponding PDMA enable bit CHENn_m (CHEN0_1 at PWM_PDMACTL[0], CHEN2_3 at PWM_PDMACTL[8] and CHEN4_5 at PWM_PDMACTL[16], where n and m denote complement pair channels) is set, the capture module will issue a request to PDMA controller when the preceding...

  • Page 438: Figure 6.8-42 Capture Pdma Operation Waveform Of Channel 0

    ISD94100 Series Technical Reference Manual Setting: CAPMOD0_1 (PWM_PDMACTL[2:1]) = 3 CAPORD0_1 (PWM_PDMACTLL[3]) = 1 CHSEL0_1 (PWM_PDMACTL[4]) = 0 CHEN0_1 CRLIF0 CFLIF0 PWM_RCAPDAT0 PWM_FCAPDAT0 PWM_PDMACAP0_1 PWM_request PDMA_ack HWDATA Figure 6.8-42 Capture PDMA Operation Waveform of Channel 0 Sep 9, 2019 Page 438 of 928 Rev1.09...

  • Page 439: Register Map

    ISD94100 Series Technical Reference Manual 6.8.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value PWM Base Address: PWM0_BA = 0x4005_8000 PWM_CTL0 PWM0_BA+0x00 R/W PWM Control Register 0 0x0000_0000 PWM_CTL1 PWM0_BA+0x04 R/W PWM Control Register 1 0x0000_0000...
  • Page 440 ISD94100 Series Technical Reference Manual Register Offset R/W Description Reset Value PWM Base Address: PWM0_BA = 0x4005_8000 PWM_PHS0_1 PWM0_BA+0x80 R/W PWM Counter Phase Register 0/1 0x0000_0000 PWM_PHS2_3 PWM0_BA+0x84 R/W PWM Counter Phase Register 2/3 0x0000_0000 PWM_PHS4_5 PWM0_BA+0x88 R/W PWM Counter Phase Register 4/5 0x0000_0000 PWM_CNT0 PWM0_BA+0x90...
  • Page 441 ISD94100 Series Technical Reference Manual Register Offset R/W Description Reset Value PWM Base Address: PWM0_BA = 0x4005_8000 PWM_FTCMPDAT2_3 PWM0_BA+0x104 R/W PWM Free Trigger Compare Register 2/3 0x0000_0000 PWM_FTCMPDAT4_5 PWM0_BA+0x108 R/W PWM Free Trigger Compare Register 4/5 0x0000_0000 PWM_SSCTL PWM0_BA+0x110 R/W PWM Synchronous Start Control Register 0x0000_0000 PWM_SSTRG PWM0_BA+0x114...
  • Page 442 ISD94100 Series Technical Reference Manual Register Offset R/W Description Reset Value PWM Base Address: PWM0_BA = 0x4005_8000 PWM_PBUF2 PWM0_BA+0x30C PWM PERIOD2 Buffer 0x0000_0000 PWM_PBUF3 PWM0_BA+0x310 PWM PERIOD3 Buffer 0x0000_0000 PWM_PBUF4 PWM0_BA+0x314 PWM PERIOD4 Buffer 0x0000_0000 PWM_PBUF5 PWM0_BA+0x318 PWM PERIOD5 Buffer 0x0000_0000 PWM_CMPBUF0 PWM0_BA+0x31C...

  • Page 443: Register Description

    ISD94100 Series Technical Reference Manual 6.8.7 Register Description PWM Control Register 0 (PWM_CTL0) Offset R/W Description Reset Value Register PWM_CTL0 PWM0_BA+0x00 R/W PWM Control Register 0 0x0000_0000 DBGTRIOFF DBGHALT Reserved GROUPEN Reserved IMMLDEN5 IMMLDEN4 IMMLDEN3 IMMLDEN2 IMMLDEN1 IMMLDEN0 Reserved WINLDEN5 WINLDEN4 WINLDEN3 WINLDEN2...
  • Page 444 ISD94100 Series Technical Reference Manual PERIOD/CMPDAT. Note: If IMMLDEN5 is enabled, WINLDEN5 and CTRLD5 will be invalid. PWM Channel 4 Immediately Load Enable Bits 0 = PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
  • Page 445 ISD94100 Series Technical Reference Manual 1 = PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success.
  • Page 446 ISD94100 Series Technical Reference Manual PWM Control Register 1 (PWM_CTL1) Offset R/W Description Reset Value Register PWM_CTL1 PWM0_BA+0x04 R/W PWM Control Register 1 0x0000_0000 Reserved OUTMODE4 OUTMODE2 OUTMODE0 Reserved CNTMODE5 CNTMODE4 CNTMODE3 CNTMODE2 CNTMODE1 CNTMODE0 Reserved CNTTYPE5 CNTTYPE4 CNTTYPE3 CNTTYPE2 CNTTYPE1 CNTTYPE0 Description...
  • Page 447 ISD94100 Series Technical Reference Manual PWM Channel 2 Counter Mode CNTMODE2 [18] 0 = Auto-reload mode. 1 = One-shot mode. PWM Channel 1 Counter Mode [17] CNTMODE1 0 = Auto-reload mode. 1 = One-shot mode. PWM Channel 0 Counter Mode [16] CNTMODE0 0 = Auto-reload mode.
  • Page 448 ISD94100 Series Technical Reference Manual PWM Synchronization Register (PWM_SYNC) Offset R/W Description Reset Value Register PWM_SYNC PWM0_BA+0x08 R/W PWM Synchronization Register 0x0000_0000 Reserved PHSDIR4 PHSDIR2 PHSDIR0 SINPINV SFLTCNT SFLTCSEL SNFLTEN Reserved SINSRC4 SINSRC2 SINSRC0 Reserved PHSEN4 PHSEN2 PHSEN0 Description Bits Reserved.
  • Page 449 ISD94100 Series Technical Reference Manual PWM0_SYNC_IN Noise Filter Enable Bits SNFLTEN [16] 0 = Noise filter of input pin PWM0_SYNC_IN is Disabled. 1 = Noise filter of input pin PWM0_SYNC_IN is Enabled. Reserved. Any values read should be ignored. When writing to this field always write with [15:14] Reserved reset value.
  • Page 450 ISD94100 Series Technical Reference Manual PWM Software Control Synchronization Register (PWM_SWSYNC) Offset R/W Description Reset Value Register PWM_SWSYNC PWM0_BA+0x0C R/W PWM Software Control Synchronization Register 0x0000_0000 Reserved Reserved Reserved Reserved SWSYNC4 SWSYNC2 SWSYNC0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:3] Reserved reset value.
  • Page 451 ISD94100 Series Technical Reference Manual PWM Clock Source Register (PWM_CLKSRC) Offset R/W Description Reset Value Register PWM_CLKSRC PWM0_BA+0x10 R/W PWM Clock Source Register 0x0000_0000 Reserved Reserved ECLKSRC4 Reserved ECLKSRC2 Reserved ECLKSRC0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:19] Reserved reset value.
  • Page 452 ISD94100 Series Technical Reference Manual PWM Clock Pre-scale Register 0_1, 2_3, 4_5 (PWM_CLKPSC0_1, 2_3, 4_5) Offset R/W Description Reset Value Register PWM_CLKPSC0_1 PWM0_BA+0x14 R/W PWM Clock Pre-scale Register 0/1 0x0000_0000 PWM_CLKPSC2_3 PWM0_BA+0x18 R/W PWM Clock Pre-scale Register 2/3 0x0000_0000 PWM_CLKPSC4_5 PWM0_BA+0x1C R/W PWM Clock Pre-scale Register 4/5 0x0000_0000...
  • Page 453 ISD94100 Series Technical Reference Manual PWM Counter Enable Register (PWM_CNTEN) Offset R/W Description Reset Value Register PWM_CNTEN PWM0_BA+0x20 R/W PWM Counter Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:6] Reserved reset value.
  • Page 454 ISD94100 Series Technical Reference Manual PWM Clear Counter Register (PWM_CNTCLR) Offset R/W Description Reset Value Register PWM_CNTCLR PWM0_BA+0x24 R/W PWM Clear Counter Register 0x0000_0000 Reserved Reserved Reserved Reserved CNTCLR5 CNTCLR4 CNTCLR3 CNTCLR2 CNTCLR1 CNTCLR0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:6] Reserved reset value.
  • Page 455 ISD94100 Series Technical Reference Manual PWM Load Register (PWM_LOAD) Offset R/W Description Reset Value Register PWM_LOAD PWM0_BA+0x28 R/W PWM Load Register 0x0000_0000 Reserved Reserved Reserved Reserved LOAD5 LOAD4 LOAD3 LOAD2 LOAD1 LOAD0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:6] Reserved reset value.
  • Page 456 ISD94100 Series Technical Reference Manual 1 = Load window is set. Note: This bit only use in window loading mode, WINLDEN3(PWM_CTL0[11]) = 1. PWM Channel 2 Re-load PWM Comparator Register (CMPDAT) Control Bit This bit is software write, hardware clear when current PWM period end. Write Operation: 0 = No effect.
  • Page 457 ISD94100 Series Technical Reference Manual PWM Period Register 0~5 (PWM_PERIOD0~5) Offset R/W Description Reset Value Register PWM_PERIOD0 PWM0_BA+0x30 R/W PWM Period Register 0 0x0000_0000 PWM_PERIOD1 PWM0_BA+0x34 R/W PWM Period Register 1 0x0000_0000 PWM_PERIOD2 PWM0_BA+0x38 R/W PWM Period Register 2 0x0000_0000 PWM_PERIOD3 PWM0_BA+0x3C R/W PWM Period Register 3...
  • Page 458 ISD94100 Series Technical Reference Manual PWM Comparator Register 0~5 (PWM_CMPDAT0~5) Offset R/W Description Reset Value Register PWM_CMPDAT0 PWM0_BA+0x50 R/W PWM Comparator Register 0 0x0000_0000 PWM_CMPDAT1 PWM0_BA+0x54 R/W PWM Comparator Register 1 0x0000_0000 PWM_CMPDAT2 PWM0_BA+0x58 R/W PWM Comparator Register 2 0x0000_0000 PWM_CMPDAT3 PWM0_BA+0x5C R/W PWM Comparator Register 3...
  • Page 459 ISD94100 Series Technical Reference Manual PWM Dead-time Control Register 0_1, 2_3, 4_5 (PWM_DTCTL0_1, 2_3, 4_5) Offset R/W Description Reset Value Register PWM_DTCTL0_1 PWM0_BA+0x70 R/W PWM Dead-Time Control Register 0/1 0x0000_0000 PWM_DTCTL2_3 PWM0_BA+0x74 R/W PWM Dead-Time Control Register 2/3 0x0000_0000 PWM_DTCTL4_5 PWM0_BA+0x78 R/W PWM Dead-Time Control Register 4/5 0x0000_0000...
  • Page 460 ISD94100 Series Technical Reference Manual PWM Counter Phase Register 0_1, 2_3, 4_5 (PWM_PHS0_1, 2_3, 4_5) Offset R/W Description Reset Value Register PWM_PHS0_1 PWM0_BA+0x80 R/W PWM Counter Phase Register 0/1 0x0000_0000 PWM_PHS2_3 PWM0_BA+0x84 R/W PWM Counter Phase Register 2/3 0x0000_0000 PWM_PHS4_5 PWM0_BA+0x88 R/W PWM Counter Phase Register 4/5 0x0000_0000...
  • Page 461 ISD94100 Series Technical Reference Manual PWM Counter Register 0~5 (PWM_CNT0~5) Offset R/W Description Reset Value Register PWM_CNT0 PWM0_BA+0x90 PWM Counter Register 0 0x0000_0000 PWM_CNT1 PWM0_BA+0x94 PWM Counter Register 1 0x0000_0000 PWM_CNT2 PWM0_BA+0x98 PWM Counter Register 2 0x0000_0000 PWM_CNT3 PWM0_BA+0x9C PWM Counter Register 3 0x0000_0000 PWM_CNT4 PWM0_BA+0xA0...
  • Page 462 ISD94100 Series Technical Reference Manual PWM Generation Register 0 (PWM_WGCTL0) Offset R/W Description Reset Value Register PWM_WGCTL0 PWM0_BA+0xB0 R/W PWM Generation Register 0 0x0000_0000 Reserved PRDPCTL5 PRDPCTL4 PRDPCTL3 PRDPCTL2 PRDPCTL1 PRDPCTL0 Reserved ZPCTL5 ZPCTL4 ZPCTL3 ZPCTL2 ZPCTL1 ZPCTL0 Description Bits Reserved.
  • Page 463 ISD94100 Series Technical Reference Manual 10 = PWM period (center) point output High. 11 = PWM period (center) point output Toggle. PWM can control output level when PWM counter count to (PERIODn+1). Note: This bit is center point control when PWM counter operating in up-down counter type. PWM Channel 1 Period (Center) Point Control 00 = Do nothing.
  • Page 464 ISD94100 Series Technical Reference Manual 00 = Do nothing. 01 = PWM zero point output Low. 10 = PWM zero point output High. 11 = PWM zero point output Toggle. PWM can control output level when PWM counter count to zero. PWM Channel 0 Zero Point Control 00 = Do nothing.
  • Page 465 ISD94100 Series Technical Reference Manual PWM Generation Register 1 (PWM_WGCTL1) Offset R/W Description Reset Value Register PWM_WGCTL1 PWM0_BA+0xB4 R/W PWM Generation Register 1 0x0000_0000 Reserved CMPDCTL5 CMPDCTL4 CMPDCTL3 CMPDCTL2 CMPDCTL1 CMPDCTL0 Reserved CMPUCTL5 CMPUCTL4 CMPUCTL3 CMPUCTL2 CMPUCTL1 CMPUCTL0 Description Bits Reserved.
  • Page 466 ISD94100 Series Technical Reference Manual 00 = Do nothing. 01 = PWM compare down point output Low. 10 = PWM compare down point output High. 11 = PWM compare down point output Toggle. PWM can control output level when PWM counter down count to CMPDAT. Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
  • Page 467 ISD94100 Series Technical Reference Manual 2, 4. PWM Channel 2 Compare Up Point Control 00 = Do nothing. 01 = PWM compare up point output Low. 10 = PWM compare up point output High. [5:4] CMPUCTL2 11 = PWM compare up point output Toggle. PWM can control output level when PWM counter up count to CMPDAT.
  • Page 468 ISD94100 Series Technical Reference Manual PWM Mask Enable Register (PWM_MSKEN) Offset R/W Description Reset Value Register PWM_MSKEN PWM0_BA+0xB8 R/W PWM Mask Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved MSKEN5 MSKEN4 MSKEN3 MSKEN2 MSKEN1 MSKEN0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:6] Reserved reset value.
  • Page 469 ISD94100 Series Technical Reference Manual PWM Channel 0 Mask Enable Bits The PWM output signal will be masked when this bit is enabled. MSKEN0 0 = PWM output signal is non-masked. 1 = PWM output signal is masked and output MSKDAT0 (PWM_MSK[0]) data. Sep 9, 2019 Page 469 of 928 Rev1.09...
  • Page 470 ISD94100 Series Technical Reference Manual PWM Mask DATA Register (PWM_MSK) Offset R/W Description Reset Value Register PWM_MSK PWM0_BA+0xBC R/W PWM Mask Data Register 0x0000_0000 Reserved Reserved Reserved Reserved MSKDAT5 MSKDAT4 MSKDAT3 MSKDAT2 MSKDAT1 MSKDAT0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:6] Reserved reset value.
  • Page 471 ISD94100 Series Technical Reference Manual PWM Brake Noise Filter Register (PWM_BNF) Offset R/W Description Reset Value Register PWM_BNF PWM0_BA+0xC0 R/W PWM Brake Noise Filter Register 0x0000_0000 Reserved Reserved BRK1PINV BRK1FCNT BRK1NFSEL BRK1NFEN BRK0PINV BRK0FCNT BRK0NFSEL BRK0NFEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write [31:16] Reserved with reset value.
  • Page 472 ISD94100 Series Technical Reference Manual 000 = Filter clock = HCLK. 001 = Filter clock = HCLK/2. 010 = Filter clock = HCLK/4. 011 = Filter clock = HCLK/8. 100 = Filter clock = HCLK/16. 101 = Filter clock = HCLK/32. 110 = Filter clock = HCLK/64.
  • Page 473 ISD94100 Series Technical Reference Manual PWM System Fail Brake Control Register (PWM_FAILBRK) Offset R/W Description Reset Value Register PWM_FAILBRK PWM0_BA+0xC4 R/W PWM System Fail Brake Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CORBRKEN RAMBRKEN BODBRKEN CSSBRKEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write [31:4] Reserved with reset value.
  • Page 474 ISD94100 Series Technical Reference Manual PWM Brake Edge Detect Control Register 0_1, 2_3, 4_5 (PWM_BRKCTL0_1, 2_3, 4_5) Offset R/W Description Reset Value Register PWM_BRKCTL0_1 PWM0_BA+0xC8 R/W PWM Brake Edge Detect Control Register 0/1 0x0000_0000 PWM_BRKCTL2_3 PWM0_BA+0xCC R/W PWM Brake Edge Detect Control Register 2/3 0x0000_0000 PWM_BRKCTL4_5 PWM0_BA+0xD0...
  • Page 475 ISD94100 Series Technical Reference Manual 11 = PWM even channel output high level when PWM0 brake event happened. Note: This register is write protected. Refer to SYS_REGLCTL register. Enable System Fail As Level-detect Brake Source (Write Protected) 0 = System Fail condition as level-detect brake source Disabled. [15] SYSLBEN 1 = System Fail condition as level-detect brake source Enabled.
  • Page 476 ISD94100 Series Technical Reference Manual PWM Pin Polar Inverse Control (PWM_POLCTL) Offset R/W Description Reset Value Register PWM_POLCTL PWM0_BA+0xD4 R/W PWM Pin Polar Inverse Register 0x0000_0000 Reserved Reserved Reserved Reserved PINV5 PINV4 PINV3 PINV2 PINV1 PINV0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write [31:6] Reserved with reset value.
  • Page 477 ISD94100 Series Technical Reference Manual PWM Output Enable Register (PWM_POEN) Offset R/W Description Reset Value Register PWM_POEN PWM0_BA+0xD8 R/W PWM Output Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved POEN5 POEN4 POEN3 POEN2 POEN1 POEN0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write [31:6] Reserved with reset value.
  • Page 478 ISD94100 Series Technical Reference Manual PWM Software Brake Control Register (PWM_SWBRK) Offset R/W Description Reset Value Register PWM_SWBRK PWM0_BA+0xDC PWM Software Brake Control Register 0x0000_0000 Reserved Reserved Reserved BRKLTRG4 BRKLTRG2 BRKLTRG0 Reserved BRKETRG4 BRKETRG2 BRKETRG0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write [31:11] Reserved with reset value.
  • Page 479 ISD94100 Series Technical Reference Manual Note: This register is write protected. Refer to SYS_REGLCTL register. Sep 9, 2019 Page 479 of 928 Rev1.09...
  • Page 480 ISD94100 Series Technical Reference Manual PWM Interrupt Enable Register 0 (PWM_INTEN0) Offset R/W Description Reset Value Register PWM_INTEN0 PWM0_BA+0xE0 R/W PWM Interrupt Enable Register 0 0x0000_0000 Reserved CMPDIEN5 CMPDIEN4 CMPDIEN3 CMPDIEN2 CMPDIEN1 CMPDIEN0 Reserved CMPUIEN5 CMPUIEN4 CMPUIEN3 CMPUIEN2 CMPUIEN1 CMPUIEN0 Reserved PIEN5 PIEN4...
  • Page 481 ISD94100 Series Technical Reference Manual PWM Channel 0 Compare Down Count Interrupt Enable Bits 0 = Compare down count interrupt Disabled. [24] CMPDIEN0 1 = Compare down count interrupt Enabled. Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
  • Page 482 ISD94100 Series Technical Reference Manual Note: When up-down counter type period point means center point. PWM Channel 3 Period Point Interrupt Enable Bits 0 = Period point interrupt Disabled. [11] PIEN3 1 = Period point interrupt Enabled. Note1: When up-down counter type period point means center point. Note2: This channels will read always 0 at complementary mode.
  • Page 483 ISD94100 Series Technical Reference Manual PWM Interrupt Enable Register 1 (PWM_INTEN1) Offset R/W Description Reset Value Register PWM_INTEN1 PWM0_BA+0xE4 R/W PWM Interrupt Enable Register 1 0x0000_0000 Reserved Reserved Reserved BRKLIEN4_5 BRKLIEN2_3 BRKLIEN0_1 Reserved BRKEIEN4_5 BRKEIEN2_3 BRKEIEN0_1 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:11] Reserved reset value.
  • Page 484 ISD94100 Series Technical Reference Manual 0 = Edge-detect Brake interrupt for channel0/1 Disabled. 1 = Edge-detect Brake interrupt for channel0/1 Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register. Sep 9, 2019 Page 484 of 928 Rev1.09...
  • Page 485 ISD94100 Series Technical Reference Manual PWM Interrupt Flag Register 0 (PWM_INTSTS0) Offset R/W Description Reset Value Register PWM_INTSTS0 PWM0_BA+0xE8 R/W PWM Interrupt Flag Register 0 0x0000_0000 Reserved CMPDIF5 CMPDIF4 CMPDIF3 CMPDIF2 CMPDIF1 CMPDIF0 Reserved CMPUIF5 CMPUIF4 CMPUIF3 CMPUIF2 CMPUIF1 CMPUIF0 Reserved PIF5 PIF4...
  • Page 486 ISD94100 Series Technical Reference Manual Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, PWM Channel 0 Compare Down Count Interrupt Flag Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT0, software can clear this bit by writing 1 to it.
  • Page 487 ISD94100 Series Technical Reference Manual PWM Channel 5 Period Point Interrupt Flag PIF5 [13] This bit is set by hardware when PWM counter reaches PWM_PERIOD5, software can write 1 to clear this bit to zero. PWM Channel 4 Period Point Interrupt Flag PIF4 [12] This bit is set by hardware when PWM counter reaches PWM_PERIOD4, software can write...
  • Page 488 ISD94100 Series Technical Reference Manual PWM Interrupt Flag Register 1 (PWM_INTSTS1) Offset R/W Description Reset Value Register PWM_INTSTS1 PWM0_BA+0xEC R/W PWM Interrupt Flag Register 1 0x0000_0000 Reserved BRKLSTS5 BRKLSTS4 BRKLSTS3 BRKLSTS2 BRKLSTS1 BRKLSTS0 Reserved BRKESTS5 BRKESTS4 BRKESTS3 BRKESTS2 BRKESTS1 BRKESTS0 Reserved BRKLIF5 BRKLIF4...
  • Page 489 ISD94100 Series Technical Reference Manual PWM Channel 1 Level-detect Brake Status (Read Only) 0 = PWM channel 1 level-detect brake state is released. 1 = When PWM channel 1 level-detect brake detects a falling edge of any enabled brake [25] BRKLSTS1 source;...
  • Page 490 ISD94100 Series Technical Reference Manual 0 = PWM channel 4 level-detect brake event do not happened. 1 = When PWM channel 4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This register is write protected. Refer to SYS_REGLCTL register. PWM Channel 3 Level-detect Brake Interrupt Flag (Write Protected) 0 = PWM channel 3 level-detect brake event do not happened.
  • Page 491 ISD94100 Series Technical Reference Manual 0 = PWM channel 1 edge-detect brake event do not happened. 1 = When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This register is write protected. Refer to SYS_REGLCTL register. PWM Channel 0 Edge-detect Brake Interrupt Flag (Write Protected) 0 = PWM channel 0 edge-detect brake event do not happened.
  • Page 492 ISD94100 Series Technical Reference Manual PWM Trigger EADC Source Select Register 0 (PWM_EADCTS0) Offset R/W Description Reset Value Register PWM_EADCTS0 PWM0_BA+0xF8 R/W PWM Trigger EADC Source Select Register 0 0x0000_0000 TRGEN3 Reserved TRGSEL3 TRGEN2 Reserved TRGSEL2 TRGEN1 Reserved TRGSEL1 TRGEN0 Reserved TRGSEL0 Description...
  • Page 493 ISD94100 Series Technical Reference Manual 0010 = PWM_CH2 zero or period point. 0011 = PWM_CH2 up-count CMPDAT point. 0100 = PWM_CH2 down-count CMPDAT point. 0101 = PWM_CH3 zero point. 0110 = PWM_CH3 period point. 0111 = PWM_CH3 zero or period point. 1000 = PWM_CH3 up-count CMPDAT point.
  • Page 494 ISD94100 Series Technical Reference Manual 1000 = PWM_CH1 up-count CMPDAT point. 1001 = PWM_CH1 down-count CMPDAT point. 1010 = PWM_CH0 up-count free CMPDAT point. 1011 = PWM_CH0 down-count free CMPDAT point. 1100 = PWM_CH2 up-count free CMPDAT point. 1101 = PWM_CH2 down-count free CMPDAT point. 1110 = PWM_CH4 up-count free CMPDAT point.
  • Page 495 ISD94100 Series Technical Reference Manual PWM Trigger EADC Source Select Register 1 (PWM_EADCTS1) Offset R/W Description Reset Value Register PWM_EADCTS1 PWM0_BA+0xFC R/W PWM Trigger EADC Source Select Register 1 0x0000_0000 Reserved Reserved TRGEN5 Reserved TRGSEL5 TRGEN4 Reserved TRGSEL4 Description Bits Reserved.
  • Page 496 ISD94100 Series Technical Reference Manual 0000 = PWM_CH4 zero point. 0001 = PWM_CH4 period point. 0010 = PWM_CH4 zero or period point. 0011 = PWM_CH4 up-count CMPDAT point. 0100 = PWM_CH4 down-count CMPDAT point. 0101 = PWM_CH5 zero point. 0110 = PWM_CH5 period point. 0111 = PWM_CH5 zero or period point.
  • Page 497 ISD94100 Series Technical Reference Manual PWM Free Trigger Compare Register 0_1, 2_3, 4_5 (PWM_FTCMPDAT0_1, 2_3, 4_5) Offset R/W Description Reset Value Register PWM_FTCMPDAT0_1 PWM0_BA+0x100 R/W PWM Free Trigger Compare Register 0/1 0x0000_0000 PWM_FTCMPDAT2_3 PWM0_BA+0x104 R/W PWM Free Trigger Compare Register 2/3 0x0000_0000 PWM_FTCMPDAT4_5 PWM0_BA+0x108...
  • Page 498 ISD94100 Series Technical Reference Manual PWM Synchronous Start Control Register (PWM_SSCTL) Offset R/W Description Reset Value Register PWM_SSCTL PWM0_BA+0x110 R/W PWM Synchronous Start Control Register 0x0000_0000 Reserved Reserved Reserved SSRC Reserved SSEN5 SSEN4 SSEN3 SSEN2 SSEN1 SSEN0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:10] Reserved reset value.
  • Page 499 ISD94100 Series Technical Reference Manual PWM Channel 1 Synchronous Start Function Enable Bits When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). SSEN1 0 = PWM synchronous start function Disabled. 1 = PWM synchronous start function Enabled.
  • Page 500 ISD94100 Series Technical Reference Manual PWM Synchronous Start Trigger Register (PWM_SSTRG) Offset R/W Description Reset Value Register PWM_SSTRG PWM0_BA+0x114 PWM Synchronous Start Trigger Register 0x0000_0000 Reserved Reserved Reserved Reserved CNTSEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:1] Reserved reset value.
  • Page 501 ISD94100 Series Technical Reference Manual PWM Status Register (PWM_STATUS) Offset R/W Description Reset Value Register PWM_STATUS PWM0_BA+0x120 R/W PWM Status Register 0x0000_0000 Reserved Reserved ADCTRGF5 ADCTRGF4 ADCTRGF3 ADCTRGF2 ADCTRGF1 ADCTRGF0 Reserved SYNCINF4 SYNCINF2 SYNCINF0 Reserved CNTMAXF5 CNTMAXF4 CNTMAXF3 CNTMAXF2 CNTMAXF1 CNTMAXF0 Description Bits...
  • Page 502 ISD94100 Series Technical Reference Manual reset value. PWM Channel 4 Input Synchronization Latched Flag [10] SYNCINF4 0 = Indicates no SYNC_IN event has occurred. 1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. PWM Channel 2 Input Synchronization Latched Flag SYNCINF2 0 = Indicates no SYNC_IN event has occurred.
  • Page 503 ISD94100 Series Technical Reference Manual PWM Capture Input Enable Register (PWM_CAPINEN) Offset R/W Description Reset Value Register PWM_CAPINEN PWM0_BA+0x200 R/W PWM Capture Input Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CAPINEN5 CAPINEN4 CAPINEN3 CAPINEN2 CAPINEN1 CAPINEN0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:6] Reserved reset value.
  • Page 504 ISD94100 Series Technical Reference Manual is always regarded as 0. 1 = PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin. Sep 9, 2019 Page 504 of 928 Rev1.09...
  • Page 505 ISD94100 Series Technical Reference Manual PWM Capture Control Register (PWM_CAPCTL) Offset R/W Description Reset Value Register PWM_CAPCTL PWM0_BA+0x204 R/W PWM Capture Control Register 0x0000_0000 Reserved FCRLDEN5 FCRLDEN4 FCRLDEN3 FCRLDEN2 FCRLDEN1 FCRLDEN0 Reserved RCRLDEN5 RCRLDEN4 RCRLDEN3 RCRLDEN2 RCRLDEN1 RCRLDEN0 Reserved CAPINV5 CAPINV4 CAPINV3 CAPINV2...
  • Page 506 ISD94100 Series Technical Reference Manual PWM Channel 4 Rising Capture Reload Enable Bits RCRLDEN4 [20] 0 = Rising capture reload counter Disabled. 1 = Rising capture reload counter Enabled. PWM Channel 3 Rising Capture Reload Enable Bits [19] RCRLDEN3 0 = Rising capture reload counter Disabled. 1 = Rising capture reload counter Enabled.
  • Page 507 ISD94100 Series Technical Reference Manual 1 = Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). PWM Channel 3 Capture Function Enable Bits 0 = Capture function Disabled.
  • Page 508 ISD94100 Series Technical Reference Manual PWM Capture Status Register (PWM_CAPSTS) Offset R/W Description Reset Value Register PWM_CAPSTS PWM0_BA+0x208 PWM Capture Status Register 0x0000_0000 Reserved Reserved Reserved CFLIFOV5 CFLIFOV4 CFLIFOV3 CFLIFOV2 CFLIFOV1 CFLIFOV0 Reserved CRLIFOV5 CRLIFOV4 CRLIFOV3 CRLIFOV2 CRLIFOV1 CRLIFOV0 Description Bits Reserved.
  • Page 509 ISD94100 Series Technical Reference Manual PWM Channel 4 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) CRLIFOV4 This flag indicates if rising latch happened when the corresponding CRLIF is 1. Note: This bit will be cleared automatically when user clear corresponding CRLIF. PWM Channel 3 Capture Rising Latch Interrupt Flag Overrun Status (Read Only) CRLIFOV3 This flag indicates if rising latch happened when the corresponding CRLIF is 1.
  • Page 510 ISD94100 Series Technical Reference Manual PWM Rising Capture Data Register 0~5 (PWM_RCAPDAT 0~5) Offset R/W Description Reset Value Register PWM_RCAPDAT0 PWM0_BA+0x20C PWM Rising Capture Data Register 0 0x0000_0000 PWM_RCAPDAT1 PWM0_BA+0x214 PWM Rising Capture Data Register 1 0x0000_0000 PWM_RCAPDAT2 PWM0_BA+0x21C PWM Rising Capture Data Register 2 0x0000_0000 PWM_RCAPDAT3 PWM0_BA+0x224...
  • Page 511 ISD94100 Series Technical Reference Manual PWM Falling Capture Data Register 0~5 (PWM_FCAPDAT 0~5) Offset R/W Description Reset Value Register PWM_FCAPDAT0 PWM0_BA+0x210 PWM Falling Capture Data Register 0 0x0000_0000 PWM_FCAPDAT1 PWM0_BA+0x218 PWM Falling Capture Data Register 1 0x0000_0000 PWM_FCAPDAT2 PWM0_BA+0x220 PWM Falling Capture Data Register 2 0x0000_0000 PWM_FCAPDAT3 PWM0_BA+0x228...
  • Page 512 ISD94100 Series Technical Reference Manual PWM PDMA Control Register (PWM_PDMACTL) Offset R/W Description Reset Value Register PWM_PDMACTL PWM0_BA+0x23C R/W PWM PDMA Control Register 0x0000_0000 Reserved Reserved CHSEL4_5 CAPORD4_5 CAPMOD4_5 CHEN4_5 Reserved CHSEL2_3 CAPORD2_3 CAPMOD2_3 CHEN2_3 Reserved CHSEL0_1 CAPORD0_1 CAPMOD0_1 CHEN0_1 Description Bits Reserved.
  • Page 513 ISD94100 Series Technical Reference Manual the first captured data transferred to memory through PDMA when CAPMOD2_3 =11. 0 = PWM_FCAPDAT2/3 is the first captured data to memory. 1 = PWM_RCAPDAT2/3 is the first captured data to memory. Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer 00 = Reserved.
  • Page 514 ISD94100 Series Technical Reference Manual PWM Capture Channel 0_1, 2_3, 4_5 PDMA Register (PWM_PDMACAP 0_1, 2_3, 4_5) Offset R/W Description Reset Value Register PWM_PDMACAP0_1 PWM0_BA+0x240 PWM Capture Channel 01 PDMA Register 0x0000_0000 PWM_PDMACAP2_3 PWM0_BA+0x244 PWM Capture Channel 23 PDMA Register 0x0000_0000 PWM_PDMACAP4_5 PWM0_BA+0x248...
  • Page 515 ISD94100 Series Technical Reference Manual PWM Capture Interrupt Enable Register (PWM_CAPIEN) Offset R/W Description Reset Value Register PWM_CAPIEN PWM0_BA+0x250 R/W PWM Capture Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved CAPFIEN5 CAPFIEN4 CAPFIEN3 CAPFIEN2 CAPFIEN1 CAPFIEN0 Reserved CAPRIEN5 CAPRIEN4 CAPRIEN3 CAPRIEN2 CAPRIEN1 CAPRIEN0 Description...
  • Page 516 ISD94100 Series Technical Reference Manual PWM Channel 0 Capture Falling Latch Interrupt Enable Bits 0 = Capture falling edge latch interrupt Disabled. CAPFIEN0 1 = Capture falling edge latch interrupt Enabled. Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
  • Page 517 ISD94100 Series Technical Reference Manual PWM Capture Interrupt Flag Register (PWM_CAPIF) Offset R/W Description Reset Value Register PWM_CAPIF PWM0_BA+0x254 R/W PWM Capture Interrupt Flag Register 0x0000_0000 Reserved Reserved Reserved CFLIF5 CFLIF4 CFLIF3 CFLIF2 CFLIF1 CFLIF0 Reserved CRLIF5 CRLIF4 CRLIF3 CRLIF2 CRLIF1 CRLIF0 Description...
  • Page 518 ISD94100 Series Technical Reference Manual This bit is writing 1 to clear. 0 = No capture falling latch condition happened. 1 = Capture falling latch condition happened, this flag will be set to high. Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
  • Page 519 ISD94100 Series Technical Reference Manual cleared by hardware after PDMA transfer data. Sep 9, 2019 Page 519 of 928 Rev1.09...
  • Page 520 ISD94100 Series Technical Reference Manual PWM Period Register Buffer 0~5 (PWM_PBUF0~5) Offset R/W Description Reset Value Register PWM_PBUF0 PWM0_BA+0x304 PWM PERIOD0 Buffer 0x0000_0000 PWM_PBUF1 PWM0_BA+0x308 PWM PERIOD1 Buffer 0x0000_0000 PWM_PBUF2 PWM0_BA+0x30C PWM PERIOD2 Buffer 0x0000_0000 PWM_PBUF3 PWM0_BA+0x310 PWM PERIOD3 Buffer 0x0000_0000 PWM_PBUF4 PWM0_BA+0x314...
  • Page 521 ISD94100 Series Technical Reference Manual PWM Comparator Register Buffer 0~5 (PWM_CMPBUF0~5) Offset R/W Description Reset Value Register PWM_CMPBUF0 PWM0_BA+0x31C PWM CMPDAT0 Buffer 0x0000_0000 PWM_CMPBUF1 PWM0_BA+0x320 PWM CMPDAT1 Buffer 0x0000_0000 PWM_CMPBUF2 PWM0_BA+0x324 PWM CMPDAT2 Buffer 0x0000_0000 PWM_CMPBUF3 PWM0_BA+0x328 PWM CMPDAT3 Buffer 0x0000_0000 PWM_CMPBUF4 PWM0_BA+0x32C...
  • Page 522 ISD94100 Series Technical Reference Manual PWM CLKPSC Buffer 0_1, 2_3, 4_5 (PWM_CPSCBUF0_1, 2_3, 4_5) Offset R/W Description Reset Value Register PWM_CPSCBUF0_1 PWM0_BA+0x334 PWM CLKPSC0_1 Buffer 0x0000_0000 PWM_CPSCBUF2_3 PWM0_BA+0x338 PWM CLKPSC2_3 Buffer 0x0000_0000 PWM_CPSCBUF4_5 PWM0_BA+0x33C PWM CLKPSC4_5 Buffer 0x0000_0000 Reserved Reserved Reserved CPSCBUF CPSCBUF...
  • Page 523 ISD94100 Series Technical Reference Manual PWM_FTCMPDAT Buffer (PWM_FTCBUF0_1,2_3,4_5) Offset R/W Description Reset Value Register PWM_FTCBUF0_1 PWM0_BA+0x340 PWM FTCMPDAT0_1 Buffer 0x0000_0000 PWM_FTCBUF2_3 PWM0_BA+0x344 PWM FTCMPDAT2_3 Buffer 0x0000_0000 PWM_FTCBUF4_5 PWM0_BA+0x348 PWM FTCMPDAT4_5 Buffer 0x0000_0000 Reserved Reserved FTCMPBUF FTCMPBUF Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:16] Reserved reset value.
  • Page 524 ISD94100 Series Technical Reference Manual PWM FTCMPDAT Indicator Register (PWM_FTCI) Offset R/W Description Reset Value Register PWM_FTCI PWM0_BA+0x34C R/W PWM FTCMPDAT Indicator Register 0x0000_0000 Reserved Reserved Reserved FTCMD4 FTCMD2 FTCMD0 Reserved FTCMU4 FTCMU2 FTCMU0 Bits Description Reserved. Any values read should be ignored. When writing to this field always write with Reserved [31:11] reset value.

  • Page 525: Watchdog Timer (Wdt)

    ISD94100 Series Technical Reference Manual 6.9 Watchdog Timer (WDT) 6.9.1 Overview The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.

  • Page 526: Functional Description

    ISD94100 Series Technical Reference Manual – Enable WDT peripheral clock in WDTCKEN (CLK_APBCLK0[0]). – Force enable WDT controller after chip power-on or reset in CWDTEN[2:0] (CWDTEN[2] is CONFIG0[31], CWDTEN[1:0] is CONFIG0[4:3]) The WDT clock control are shown in Figure 6.9-2 WDTSEL (CLK_CLKSEL1[1:0]) WDTCKEN (CLK_APBCLK0[0]) 10 kHz (LIRC)

  • Page 527: Figure 6.9-3 Watchdog Timer Time-Out Interval And Reset Period Timing

    ISD94100 Series Technical Reference Manual (3/18/130/1026) * T (3/18/130/1026) * T (3/18/130/1026) * T (3/18/130/1026) * T (3/18/130/1026) * T Table 6.9.5-1 Watchdog Timer Time-out Interval Period Selection RSTF = 1 IF = 1 (if RSTEN = 1) WDT_CLK RSTEN (WDT_CTL[1]) RSTD (WDT_CTL[3])
  • Page 528 ISD94100 Series Technical Reference Manual Sep 9, 2019 Page 528 of 928 Rev1.09...

  • Page 529: Register Map

    ISD94100 Series Technical Reference Manual 6.9.6 Register Map R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register WDT Base Address: WDT_BA = 0x4004_0000 WDT_CTL WDT_BA+0x00 R/W WDT Control Register 0x0000_07X0 WDT_ALTCTL WDT_BA+0x04 R/W WDT Alternative Control Register 0x0000_0000 Note:...

  • Page 530: Register Description

    ISD94100 Series Technical Reference Manual 6.9.7 Register Description WDT Control Register (WDT_CTL) Offset R/W Description Reset Value Register WDT_CTL WDT_BA+0x00 R/W WDT Control Register 0x0000_07X0 ICEDEBUG Reserved Reserved Reserved TOUTSEL WDTEN INTEN WKEN RSTF RSTEN RSTCNT Description Bits ICE Debug Mode Acknowledge Disable Control (Write Protected) 0 = ICE debug mode acknowledgement affects WDT counting.
  • Page 531 ISD94100 Series Technical Reference Manual configure to 111, this bit is forced as 1 and user cannot change this bit to 0. WDT Time-out Interrupt Enable Control (Write Protected) If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. 0 = WDT time-out interrupt Disabled.
  • Page 532 ISD94100 Series Technical Reference Manual WDT Alternative Control Register (WDT_ALTCTL) Register Offset R/W Description Reset Value WDT_ALTCTL WDT_BA+0x04 R/W WDT Alternative Control Register 0x0000_0000 Reserved Reserved Reserved Reserved RSTDSEL Description Bits Reserved. Any values read should be ignored. When writing to this field always write [31:2] Reserved with reset value.

  • Page 533: Window Watchdog Timer (Wwdt)

    ISD94100 Series Technical Reference Manual 6.10 Window Watchdog Timer (WWDT) 6.10.1 Overview The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.10.2 Features ...

  • Page 534: Basic Configuration

    ISD94100 Series Technical Reference Manual 6.10.4 Basic Configuration  Clock source configuration – Select the source of WWDT peripheral clock in WWDTSEL (CLK_CLKSEL1[31:30]) – Enable WWDT peripheral clock in WDTCKEN (CLK_APBCLK0[0]). The WWDT clock control are shown in Figure 6.10-2. WWDTSEL (CLK_CLKSEL1[31:30]) WDTCKEN (CLK_APBCLK0[0]) 10 kHz (LIRC)

  • Page 535: Figure 6.10-3 Wwdt Reset And Reload Behavior

    ISD94100 Series Technical Reference Manual 1100 768 * 64 * T 4.9152 s WWDT 1101 1024 1024 * 64 * T 6.5536 s WWDT 1110 1536 1536 * 64 * T 9.8304 s WWDT 1111 2048 2048 * 64 * T 13.1072 s WWDT Table 6.10.5-1 WWDT Prescaler Value Selection...

  • Page 536: Figure 6.10-4 Wwdt Reload Counter When Cntdat > Cmpdat

    ISD94100 Series Technical Reference Manual If current CNTDAT (WWDT_CNT[5:0]) is larger than CMPDAT (WWDT_CTL[21:16]) and user writes 0x00005AA5 to the WWDT_RLDCNT register, the WWDT reset system signal will be generated immediately to cause chip reset also. The waveform of WWDT reload counter when CNTDAT >...

  • Page 537: Figure 6.10-5 Wwdt Reload Counter When Wwdt_Cnt < Wincmp

    ISD94100 Series Technical Reference Manual Figure 6.10-5 WWDT Reload Counter When WWDT_CNT < WINCMP WWDTIF = 1 (if CMPDAT = 0x10) WWDTRF = 1 WWDT WWDT_CLK 14 13 12 11 10 0F 0E 02 01 00 WWDTVAL WWDTIF (WWDT_STATUS[0]) WWDTRF (WWDT_STATUS[1]) Note : PSCSEL (WWDT_CTL[11:8]) = 0x0, CMPDAT (WWDT_CTL[21:16]) = 0x10 Figure 6.10-6 WWDT Interrupt and Reset Signals...

  • Page 538: Register Map

    ISD94100 Series Technical Reference Manual 6.10.6 Register Map R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register WWDT Base Address: WWDT_BA = 0x4004_0100 WWDT_RLDCNT WWDT_BA+0x00 WWDT Reload Counter Register 0x0000_0000 WWDT_CTL WWDT_BA+0x04 R/W WWDT Control Register 0x003F_0800 WWDT_STATUS...

  • Page 539: Register Description

    ISD94100 Series Technical Reference Manual 6.10.7 Register Description WWDT Reload Counter Register (WWDT_RLDCNT) Offset R/W Description Reset Value Register WWDT_RLDCNT WWDT_BA+0x00 WWDT Reload Counter Register 0x0000_0000 RLDCNT RLDCNT RLDCNT RLDCNT Description Bits WWDT Reload Counter Register Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. [31:0] Note: User can only write WWDT_RLDCNT register to reload WWDT counter value RLDCNT...
  • Page 540 ISD94100 Series Technical Reference Manual WWDT Control Register (WWDT_CTL) Offset R/W Description Reset Value Register WWDT_CTL WWDT_BA+0x04 R/W WWDT Control Register 0x003F_0800 Note: This register can be write only one time after chip is powered on or reset. ICEDEBUG Reserved Reserved CMPDAT Reserved...
  • Page 541 ISD94100 Series Technical Reference Manual 1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. 1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. 1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. 1110 = Pre-scale is 1536;...
  • Page 542 ISD94100 Series Technical Reference Manual WWDT Status Register (WWDT_STATUS) Offset R/W Description Reset Value Register WWDT_STATUS WWDT_BA+0x08 R/W WWDT Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WWDTRF WWDTIF Description Bits Reserved. Any values read should be ignored. When writing to this field always write [31:2] Reserved with reset value.
  • Page 543 ISD94100 Series Technical Reference Manual WWDT Counter Value Register (WWDT_CNT) Offset R/W Description Reset Value Register WWDT_CNT WWDT_BA+0x0C WWDT Counter Value Register 0x0000_003F Reserved Reserved Reserved Reserved CNTDAT Description Bits Reserved. Any values read should be ignored. When writing to this field always write [31:6] Reserved with reset value.

  • Page 544: Real Time Clock (Rtc)

    ISD94100 Series Technical Reference Manual 6.11 Real Time Clock (RTC) 6.11.1 Overview The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers programmable time tick and alarm match interrupts. The data format of time and calendar message are expressed in BCD format.

  • Page 545: Block Diagram

    ISD94100 Series Technical Reference Manual 6.11.3 Block Diagram The RTC block diagram is shown below. Time Alarm Calendar Alarm Time Alarm Calendar Mask Register Mask Register Register Alarm Register (RTC_TAMSK) (RTC_CAMSK) (RTC_TALM) (RTC_CALM) ALMIEN (RTC_INTEN[0]) Calendar Time Loading Loading Alarm Interrupt Compare Register Register...

  • Page 546: Table 6.11.5-1 Rtc Read/Write Enable

    ISD94100 Series Technical Reference Manual 6.11.5.2 RTC Read/Write Enable If RWENF(RTC_RWEN[16]) bit is read as 1, it means the RTC registers are read/write accessible. When executing write RTC register command exceed 6 times within 1120 PCLK cycles, the RTCBUSY(RTC_RWEN[24]) flag will be set 1 and RWENF(RTC_RWEN[16]) will be clear to 0. The RTC control registers access attribute when RWENF is 1 and 0 are shown in Table 6.11.5-1.

  • Page 547: Table 6.11.5-2 12/24 Hour Time Scale Selection

    ISD94100 Series Technical Reference Manual 6.11.5.4 Time and Calendar counter RTC_TIME and RTC_CAL are used to load the real time and calendar. RTC_TALM and RTC_CALM are used for setup alarm time and calendar. 6.11.5.5 12/24 hour Time Scale Selection The 12/24 hour time scale selection depends on 24HEN (RTC_CLKFMT[0]). When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication, if RTC_TIME[21] is 1, it indicates PM time message and RTC_TIME[21] is 0 indicates AM time message.

  • Page 548: Table 6.11.5-3 Registers Value After Power-On

    ISD94100 Series Technical Reference Manual The RTC controller provides time alarm mask register (RTC_TAMSK register) and calendar alarm mask register (RTC_CAMSK register) to mask the specified digit and generate periodic interrupt without changing the alarm match condition in RTC_TALM and RTC_CALM registers in each alarm interrupt service routine.

  • Page 549: Register Map

    ISD94100 Series Technical Reference Manual 6.11.6 Register Map R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register RTC Base Address: RTC_BA = 0x4004_1000 RTC_INIT RTC_BA+0x00 R/W RTC Initiation Register 0x0000_0000 RTC_RWEN RTC_BA+0x04 R/W RTC Access Enable Register 0x0000_0000 RTC_FREQADJ...

  • Page 550: Register Description

    ISD94100 Series Technical Reference Manual 6.11.7 Register Description RTC Initiation Register (RTC_INIT) Offset R/W Description Reset Value Register RTC_INIT RTC_BA+0x00 R/W RTC Initiation Register 0x0000_0000 INIT INIT INIT INIT INIT/ACTIVE Description Bits RTC Initiation (Write Only) When RTC block is powered on, RTC is at reset state. User has to write a number (0x [31:1] INIT[31:1] a5eb1357) to INIT to make RTC leaving reset state.
  • Page 551 ISD94100 Series Technical Reference Manual RTC Access Enable Register (RTC_RWEN) Offset R/W Description Reset Value Register RTC_RWEN RTC_BA+0x04 R/W RTC Access Enable Register 0x0000_0000 Reserved RTCBUSY Reserved RWENF Reserved Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:25] Reserved reset value.
  • Page 552 ISD94100 Series Technical Reference Manual RTC Frequency Compensation Register (RTC_FREQADJ) Offset R/W Description Reset Value Register RTC_FREQADJ RTC_BA+0x08 R/W RTC Frequency Compensation Register 0x0020_0000 Reserved Reserved FREQADJ FREQADJ FREQADJ Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:22] Reserved reset value.
  • Page 553 ISD94100 Series Technical Reference Manual RTC Time Loading Register (RTC_TIME) Offset R/W Description Reset Value Register RTC_TIME RTC_BA+0x0C R/W RTC Time Loading Register 0x0000_0000 Reserved Reserved TENHR Reserved TENMIN Reserved TENSEC Description Bits Reserved. Any values read should be ignored. When writing to this field always write with reset [31:22] Reserved value.
  • Page 554 ISD94100 Series Technical Reference Manual RTC Calendar Loading Register (RTC_CAL) Offset R/W Description Reset Value Register RTC_CAL RTC_BA+0x10 R/W RTC Calendar Loading Register 0x0015_0808 Reserved TENYEAR YEAR Reserved TENMON Reserved TENDAY Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:24] Reserved reset value.
  • Page 555 ISD94100 Series Technical Reference Manual RTC Time Scale Selection Register (RTC_CLKFMT) Offset R/W Description Reset Value Register RTC_CLKFMT RTC_BA+0x14 R/W RTC Time Scale Selection Register 0x0000_0001 Reserved Reserved Reserved Reserved 24HEN Bits Description Reserved. Any values read should be ignored. When writing to this field always write with [31:1] Reserved reset value.
  • Page 556 ISD94100 Series Technical Reference Manual RTC Day of the Week Register (RTC_WEEKDAY) Offset R/W Description Reset Value Register RTC_WEEKDAY RTC_BA+0x18 R/W RTC Day of the Week Register 0x0000_0006 Reserved Reserved Reserved Reserved WEEKDAY Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:3] Reserved reset value.
  • Page 557 ISD94100 Series Technical Reference Manual RTC Time Alarm Register (RTC_TALM) Offset R/W Description Reset Value Register RTC_TALM RTC_BA+0x1C R/W RTC Time Alarm Register 0x0000_0000 Reserved Reserved TENHR Reserved TENMIN Reserved TENSEC Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:22] Reserved reset value.
  • Page 558 ISD94100 Series Technical Reference Manual RTC Calendar Alarm Register (RTC_CALM) Offset R/W Description Reset Value Register RTC_CALM RTC_BA+0x20 R/W RTC Calendar Alarm Register 0x0000_0000 Reserved TENYEAR YEAR Reserved TENMON Reserved TENDAY Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:24] Reserved reset value.
  • Page 559 ISD94100 Series Technical Reference Manual RTC Leap Year Indication Register (RTC_LEAPYEAR) Offset R/W Description Reset Value Register RTC_LEAPYEAR RTC_BA+0x24 RTC Leap Year Indicator Register 0x0000_0000 Reserved Reserved Reserved Reserved LEAPYEAR Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:1] Reserved reset value.
  • Page 560 ISD94100 Series Technical Reference Manual RTC Interrupt Enable Register (RTC_INTEN) Offset R/W Description Reset Value Register RTC_INTEN RTC_BA+0x28 R/W RTC Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved TICKIEN ALMIEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:2] Reserved reset value.
  • Page 561 ISD94100 Series Technical Reference Manual RTC Interrupt Status Register (RTC_INTSTS) Offset R/W Description Reset Value Register RTC_INTSTS RTC_BA+0x2C R/W RTC Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved TICKIF ALMIF Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:2] Reserved reset value.
  • Page 562 ISD94100 Series Technical Reference Manual RTC Time Tick Register (RTC_TICK) Offset R/W Description Reset Value Register RTC_TICK RTC_BA+0x30 R/W RTC Time Tick Register 0x0000_0000 Reserved Reserved Reserved Reserved TICK Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:3] Reserved reset value.
  • Page 563 ISD94100 Series Technical Reference Manual RTC Time Alarm MASK Register (RTC_TAMSK) Offset R/W Description Reset Value Register RTC_TAMSK RTC_BA+0x34 R/W RTC Time Alarm Mask Register 0x0000_0000 Reserved Reserved Reserved Reserved MTENHR MTENMIN MMIN MTENSEC MSEC Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:6] Reserved reset value.
  • Page 564 ISD94100 Series Technical Reference Manual RTC Calendar Alarm MASK Register (RTC_CAMSK) Offset R/W Description Reset Value Register RTC_CAMSK RTC_BA+0x38 R/W RTC Calendar Alarm Mask Register 0x0000_0000 Reserved Reserved Reserved Reserved MTENYEAR MYEAR MTENMON MMON MTENDAY MDAY Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:6] Reserved reset value.
  • Page 565 ISD94100 Series Technical Reference Manual RTC 32K Oscillator Control Register (RTC_LXTCTL) Offset R/W Description Reset Value Register RTC_LXTCTL RTC_BA+0x100 R/W RTC 32.768 kHz Oscillator Control Register 0x0000_000E Reserved Reserved Reserved Reserved GAIN Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:3] Reserved reset value.

  • Page 566: Uart Interface Controller (Uart)

    ISD94100 Series Technical Reference Manual 6.12 UART Interface Controller (UART) 6.12.1 Overview The ISD94100 series is equipped with one Universal Asynchronous Receiver/Transmitters (UART) port, which offers a mean of full-duplex asynchronous communication with external device. The ISD94100 series UART controller also supports RS-485 standard. 6.12.2 Features ...

  • Page 567: Block Diagram

    ISD94100 Series Technical Reference Manual √ Incoming Data Wake-up RX FIFO reached threshold √ Wake-up RS-485 Address Match (AAD √ mode) Wake-up √ Auto-Baud Rate Measurement STOP Bit Length 1, 1.5, 2 bit Word Length 5, 6, 7, 8 bits √...

  • Page 568: Figure 6.12-2 Uart Block Diagram

    ISD94100 Series Technical Reference Manual APB_BUS UART Interrupt Status & Control Status & Control Interrupt FIFO & Line RX_FIFO TX_FIFO Control Control and Status & status Register Baud Out Baud Out TX Shift Register RX Shift Register MODEM Control and Status Register UART0_nRTS UART0_nCTS...
  • Page 569 ISD94100 Series Technical Reference Manual Each block is described in detail as follows: TX_FIFO The transmitter is buffered with a 16 bytes FIFO to reduce the number of interrupts presented to the CPU. RX_FIFO The receiver is buffered with a 16 bytes FIFO (plus three error bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4])) to reduce the number of interrupts presented to the CPU.

  • Page 570: Basic Configuration

    ISD94100 Series Technical Reference Manual RLSINT Receive Line Status Interrupt (parity error or frame error or break error). MODEMINT MODEM Status Interrupt. RXTOINT Receiver Buffer Time-out Interrupt. BUFERRINT Buffer Error Interrupt. WKINT Wake-up Interrupt. ABRINT Auto-Baud Rate Interrupt. Table 6.12.3-1 UART Interrupt 6.12.4 Basic Configuration ...

  • Page 571: Functional Description

    ISD94100 Series Technical Reference Manual UART0_TXD Output UART0 transmit UART0_RXD Input UART0 receive UART0_nCTS Input UART0 modem clear to send UART0_nRTS Output UART0 modem request to send Table 6.12.4-1 UART Interface Controller Pin 6.12.5 Functional Description The ISD94100 series UART controller supports four function modes including UART and RS-485. The current function mode is selected by UART_FUNCSEL register.

  • Page 572: Table 6.12.5-2 Uart Controller Baud Rate Parameter Setting Example Table

    ISD94100 Series Technical Reference Manual 460800 Not recommended BRD=0, EDIVM1 =13 BRD=24 230400 Not recommended BRD =2, EDIVM1 =13 BRD =50 115200 Not recommended BRD =6, EDIVM1 =13 BRD =102 57600 BRD =11 BRD =14, EDIVM1 =13 BRD =206 38400 BRD =18 BRD =22, EDIVM1 =13 BRD =311...

  • Page 573: Table 6.12.5-4 Baud Rate Compensation Example Table 1

    ISD94100 Series Technical Reference Manual if the baud divider is set 1 (3 peripheral clock/bit), the inaccuracy of each bit is -0.413 peripheral clock and BRCOMPDEC =0, Name Total INACCURACY BRCOMP Compensated Final Inaccuracy Start -0.413 -0.413 UART_DAT[0] -0.826(-0.413-0.413) 0.174 UART_DAT[1] -0.239(0.174-0.413) -0.239...

  • Page 574: Figure 6.12-3 Auto-Baud Rate Measurement

    ISD94100 Series Technical Reference Manual 6.12.5.3 UART Controller Auto-Baud Rate Function Mode The ISD94100 Auto-Baud Rate function measures the baud rate of in-coming data from UART RX pin automatically. When the Auto-Baud Rate measurement is finished, the measuring baud rate is loaded into BRD (UART_BAUD[15:0]).

  • Page 575: Figure 6.12-4 Transmit Delay Time Operation

    ISD94100 Series Technical Reference Manual ABRDIF (UART_FIFOSTS[1]) is set, the auto-baud rate measurement is finished. Operate UART transmit and receive action. ABRDTOIF (UART_FIFOSTS[2]) is set, if auto-baud rate counter is overflow. Go to Step 3. 6.12.5.4 UART Controller Transmit Delay Time Value By configuring DLY (UART_TOUT [15:8]), transfer delay time can be added between the last stop bit and next start bit in transmission, shown in Figure 6.12-4.

  • Page 576: Figure 6.12-5 Uart Ncts Wake-Up Case1

    ISD94100 Series Technical Reference Manual nCTS Wake-up Case 1 (nCTS transition from low to high) Power-down mode CPU run stable count HCLK nCTS CTSWKF CTSACTLV (UART_MODEMSTS[8]) = 0 Note: Stable count means HCLK source recovery stable count. Figure 6.12-5 UART nCTS Wake-up Case1 nCTS Wake-up Case 2 (nCTS transition from high to low) Power-down mode CPU run...

  • Page 577: Figure 6.12-7 Uart Data Wake-Up

    ISD94100 Series Technical Reference Manual Power-down mode stable count CPU run HCLK UART_CLK stable count UART0_CLK start UART0_RXD pin DATWKF Note1: Stable count means HCLK source recovery stable count. Note2: UART0_CLK stable count means UART clock source recovery stable count. Figure 6.12-7 UART Data Wake-up RX FIFO reaching threshold wake-up: To setup the RX FIFO Reached Threshold Wake-up function, configure the following bits:...

  • Page 578: Figure 6.12-9 Uart Rs-485 Aad Mode Address Match Wake-Up

    ISD94100 Series Technical Reference Manual stable count Power-down mode HCLK Start UART0_RXD pin Address Match RS485WKF Note: Stable count means HCLK source recovery stable count. Figure 6.12-9 UART RS-485 AAD Mode Address Match Wake-up RX FIFO threshold time-out wake-up: RX FIFO Threshold Time-out Wake-up function can wake up the system if the device has not received certain amount of data within specified time.
  • Page 579 ISD94100 Series Technical Reference Manual 6.12.5.7 UART Controller Interrupt and Status The ISD94100 series UART controller supports ten kinds of interrupts listed below:  Receive Data Available Interrupt (RDAINT)  Transmit Holding Register Empty Interrupt (THERINT)  Transmitter Empty Interrupt (TXENDIF) ...

  • Page 580: Table 6.12.5-6 Uart Controller Interrupt Source And Flag List

    ISD94100 Series Technical Reference Manual Table 6.12.5-6 describes the interrupt sources and flags. When an interrupt occurred, its corresponding flag will be raised (set). Software should clear the interrupt flag after the interrupt is generated. Writing 1 (to flag) clears the interrupt flag. Interrupt Enable Interrupt Interrupt Flag...

  • Page 581: Table 6.12.5-7 Uart Line Control Of Word And Stop Length Setting

    ISD94100 Series Technical Reference Manual auto-flow control that provides programmable nRTS flow control trigger level. The number of data bytes in RX FIFO is equal to or greater than RTSTRGLV (UART_FIFO[19:16]), the nRTS is de- asserted. UART Line Control Function The UART controller supports fully programmable serial-interface characteristics via UART_LINE register.

  • Page 582: Figure 6.12-11 Auto-Flow Control Block Diagram

    ISD94100 Series Technical Reference Manual UART Auto-Flow Control Function The UART supports auto-flow control function that uses two signals, nCTS (clear-to-send) and nRTS (request-to-send), to control the flow of data transfer between the UART and an external devices (e.g. Modem). When auto-flow is enabled, the UART is not allowed to receive data until the UART asserts nRTS to external device.

  • Page 583: Figure 6.12-12 Uart Ncts Auto-Flow Control Enabled

    ISD94100 Series Technical Reference Manual UART0_nCTS pin input status of UART function mode CTSACTLV=0 CTSSTS (UART_MODEMSTS[4]) Active UART0_nCTS pin Inactive input CTSACTLV=1 (default) TX stop MODEMINT interrupt MODEMINT interrupt CTSDETF Clear by softwave Clear by softwave UART0_TXD pin Start Stop output Idle Idle...

  • Page 584: Figure 6.12-14 Uart Nrts Auto-Flow With Software Control

    ISD94100 Series Technical Reference Manual is directly controlled by software programming of RTS(UART_MODEM[1]) control bit. Setting RTSACTLV (UART_MODEM[9]) can control the UART0_nRTS pin output is inverse or non- inverse from RTS (UART_MODEM[1]) control bit. User can read the RTSSTS (UART_MODEM[13]) bit to get real nRTS pin output voltage logic status.
  • Page 585 ISD94100 Series Technical Reference Manual RXOFF (UART_FIFO [8]) then enable RS485NMM (UART_ALTCTL[8]) and the receiver will received any data. If an address byte is detected (bit 9 = 1), it will generate an interrupt to CPU and RXOFF (UART_FIFO[8]) can decide whether accepting the following data bytes are stored in the RX FIFO. If software disables receiver by setting RXOFF (UART_FIFO[8]) register, when a next address byte is detected, the controller will clear the RXOFF (UART_FIFO[8]) bit and the address byte data will be stored in the RX FIFO.

  • Page 586: Figure 6.12-15 Rs-485 Nrts Driving Level In Auto Direction Mode

    ISD94100 Series Technical Reference Manual nRTS pin output status of RS-485 function mode (RS-485 AUD mode enabled) Start Stop TX pin output RTSSTS RTSACTLV = 0 (UART_MODEM[13]) Driver Enable nRTS pin output RTSACTLV = 1 (default) Note: RS485AUD(UART_ALTCTL[10]) = 1, the nRTS pin output by hardware control only. Figure 6.12-15 RS-485 nRTS Driving Level in Auto Direction Mode Figure 6.12-16 demonstrates the RS-485 nRTS driving level in software control (RS485AUD (UART_ALTCTL[10])=0).

  • Page 587: Figure 6.12-17 Structure Of Rs-485 Frame

    ISD94100 Series Technical Reference Manual Determine auto direction control by programming RS485AUD (UART_ALTCTL[10]). Differential Bus Driver Enable nRTS UART / RS- 485 Controller RS- 485 Transceiver Start Stop TX pin output RTSSTS Driver Enable (UART_MODEM[13]) Note: RS485AUD(UART_ALTCTL[10]) must be set to 1, and RTSACTLV(UART_MODEM[9]) must be set to Figure 6.12-17 Structure of RS-485 Frame 6.12.5.10 PDMA Transfer Function UART controller supports PDMA transfer function.

  • Page 588: Register Map

    ISD94100 Series Technical Reference Manual 6.12.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value UART Base Address: UART0_BA = 0x4007_0000 UART_DAT UART0_BA+0x00 R/W UART Receive/Transmit Buffer Register 0x0000_0000 UART_INTEN UART0_BA+0x04 R/W UART Interrupt Enable Register 0x0000_0000...

  • Page 589: Register Description

    ISD94100 Series Technical Reference Manual 6.12.7 Register Description UART Receive/Transmit Buffer Register (UART_DAT) Offset R/W Description Reset Value Register UART_DAT UART0_BA+0x00 R/W UART Receive/Transmit Buffer Register 0x0000_0000 Reserved Reserved Reserved PARITY Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 590 ISD94100 Series Technical Reference Manual UART Interrupt Enable Register (UART_INTEN) Offset R/W Description Reset Value Register UART_INTEN UART0_BA+0x04 R/W UART Interrupt Enable Register 0x0000_0000 Reserved Reserved TXENDIEN Reserved ABRIEN Reserved RXPDMAEN TXPDMAEN ATOCTSEN ATORTSEN TOCNTEN Reserved Reserved WKIEN BUFERRIEN RXTOIEN MODEMIEN RLSIEN THREIEN...
  • Page 591 ISD94100 Series Technical Reference Manual 1 = TX PDMA Enabled. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA transmit request operation is stop.
  • Page 592 ISD94100 Series Technical Reference Manual UART FIFO Control Register (UART_FIFO) Offset R/W Description Reset Value Register UART_FIFO UART0_BA+0x08 R/W UART FIFO Control Register 0x0000_0101 Reserved Reserved RTSTRGLV Reserved RXOFF RFITL Reserved TXRST RXRST Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:20] Reserved reset value.
  • Page 593 ISD94100 Series Technical Reference Manual reset value. TX Field Software Reset When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. 0 = No effect. TXRST 1 = Reset the TX internal state machine and pointers. Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
  • Page 594 ISD94100 Series Technical Reference Manual UART Line Control Register (UART_LINE) Offset R/W Description Reset Value Register UART_LINE UART0_BA+0x0C R/W UART Line Control Register 0x0000_0000 Reserved Reserved Reserved RXDINV TXDINV Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:10] Reserved reset value.
  • Page 595 ISD94100 Series Technical Reference Manual 1 = Break Control Enabled. Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
  • Page 596 ISD94100 Series Technical Reference Manual UART Modem Control Register (UART_MODEM) Offset R/W Description Reset Value Register UART_MODEM UART0_BA+0x10 R/W UART Modem Control Register 0x0000_0200 Reserved Reserved Reserved RTSSTS Reserved RTSACTLV Reserved Reserved Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:14] Reserved reset value.
  • Page 597 ISD94100 Series Technical Reference Manual Reserved. Any values read should be ignored. When writing to this field always write with Reserved reset value. Sep 9, 2019 Page 597 of 928 Rev1.09...
  • Page 598 ISD94100 Series Technical Reference Manual UART Modem Status Register (UART_MODEMSTS) Offset R/W Description Reset Value Register UART_MODEMSTS UART0_BA+0x14 R/W UART Modem Status Register 0x0000_0110 Reserved Reserved Reserved CTSACTLV Reserved CTSSTS Reserved CTSDETF Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 599 ISD94100 Series Technical Reference Manual UART FIFO Status Register (UART_FIFOSTS) Offset R/W Description Reset Value Register UART_FIFOSTS UART0_BA+0x18 R/W UART FIFO Status Register 0xB040_4000 TXRXACT Reserved RXIDLE TXEMPTYF Reserved TXOVIF TXFULL TXEMPTY Reserved TXPTR RXFULL RXEMPTY Reserved RXPTR Reserved ADDRDETF ABRDTOIF ABRDIF RXOVIF...
  • Page 600 ISD94100 Series Technical Reference Manual Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. 0 = TX FIFO is not full. [23] TXFULL 1 = TX FIFO is full. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
  • Page 601 ISD94100 Series Technical Reference Manual 0 = No Break interrupt is generated. 1 = Break interrupt is generated. Note: This bit can be cleared by writing “1” to it. Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid “stop bit” (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
  • Page 602 ISD94100 Series Technical Reference Manual UART Interrupt Status Register (UART_INTSTS) Offset R/W Description Reset Value Register UART_INTSTS UART0_BA+0x1C R/W UART Interrupt Status Register 0x0040_0002 ABRINT TXENDINT HWBUFEINT HWTOINT HWMODINT HWRLSINT Reserved Reserved TXENDIF HWBUFEIF HWTOIF HWMODIF HWRLSIF Reserved Reserved WKINT BUFERRINT RXTOINT MODEMINT...
  • Page 603 ISD94100 Series Technical Reference Manual set to 1. 0 = No RLS interrupt is generated in PDMA mode. 1 = RLS interrupt is generated in PDMA mode. Reserved. Any values read should be ignored. When writing to this field always write with Reserved [25:23] reset value.
  • Page 604 ISD94100 Series Technical Reference Manual reset value. UART Wake-up Interrupt Indicator (Read Only) This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to [14] WKINT 0 = No UART wake-up interrupt is generated. 1 = UART wake-up interrupt is generated. Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
  • Page 605 ISD94100 Series Technical Reference Manual RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. 0 = No buffer error interrupt flag is generated. 1 = Buffer error interrupt flag is generated.
  • Page 606 ISD94100 Series Technical Reference Manual UART Time-out Register (UART_TOUT) Offset R/W Description Reset Value Register UART_TOUT UART0_BA+0x20 R/W UART Time-out Register 0x0000_0000 Reserved Reserved TOIC Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:16] Reserved reset value.
  • Page 607 ISD94100 Series Technical Reference Manual UART Baud Rate Divider Register (UART_BAUD) Offset R/W Description Reset Value Register UART_BAUD UART0_BA+0x24 R/W UART Baud Rate Divider Register 0x0F00_0000 Reserved BAUDM1 BAUDM0 EDIVM1 Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:30] Reserved reset value.
  • Page 608 ISD94100 Series Technical Reference Manual UART Alternate Control/Status Register (UART_ALTCTL) Offset R/W Description Reset Value Register UART_ALTCTL UART0_BA+0x2C R/W UART Alternate Control/Status Register 0x0000_000C ADDRMV Reserved ABRDBITS ABRDEN ABRIF Reserved ADDRDEN Reserved RS485AUD RS485AAD RS485NMM Reserved Description Bits Address Match Value [31:24] ADDRMV This field contains the RS-485 address match values.
  • Page 609 ISD94100 Series Technical Reference Manual 0 = Address detection mode Disabled. 1 = Address detection mode Enabled. Note: This bit is used for RS-485 any operation mode. Reserved. Any values read should be ignored. When writing to this field always write with Reserved [14:11] reset value.
  • Page 610 ISD94100 Series Technical Reference Manual UART Function Select Register (UART_FUNCSEL) Offset R/W Description Reset Value Register UART_FUNCSEL UART0_BA+0x30 R/W UART Function Select Register 0x0000_0000 Reserved Reserved Reserved Reserved TXRXDIS Reserved FUNCSEL Bits Description Reserved. Any values read should be ignored. When writing to this field always write with [31:4] Reserved reset value.
  • Page 611 ISD94100 Series Technical Reference Manual UART Baud Rate Compensation Register (UART_BRCOMP) Offset R/W Description Reset Value Register UART_BRCOMP UART0_BA+0x3C R/W UART Baud Rate Compensation Register 0x0000_0000 BRCOMPDEC Reserved Reserved Reserved BRCOMP BRCOMP Description Bits Baud Rate Compensation Decrease [31] BRCOMPDEC 0 = Positive (increase one module clock) compensation for each compensated bit.
  • Page 612 ISD94100 Series Technical Reference Manual UART Wake-up Control Register (UART_WKCTL) Offset R/W Description Reset Value Register UART_WKCTL UART0_BA+0x40 R/W UART Wake-up Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WKTOUTEN WKRS485EN WKRFRTEN WKDATEN WKCTSEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:5] Reserved reset value.
  • Page 613 ISD94100 Series Technical Reference Manual external. nCTS change will wake-up system from Power-down mode. Sep 9, 2019 Page 613 of 928 Rev1.09...
  • Page 614 ISD94100 Series Technical Reference Manual UART Wake-up Status Register (UART_WKSTS) Offset R/W Description Reset Value Register UART_WKSTS UART0_BA+0x44 R/W UART Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved TOUTWKF RS485WKF RFRTWKF DATWKF CTSWKF Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:5] Reserved reset value.
  • Page 615 ISD94100 Series Technical Reference Manual Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to ‘1’. Note2: This bit can be cleared by writing ‘1’ to it. nCTS Wake-up Flag This bit is set if chip wake-up from power-down state by nCTS wake-up. 0 = Chip stays in power-down state.
  • Page 616 ISD94100 Series Technical Reference Manual UART Incoming Data Wake-up Compensation Register (UART_DWKCOMP) Offset R/W Description Reset Value Register UART_DWKCOMP UART0_BA+0x48 R/W UART Incoming Data Wake-up Compensation Register 0x0000_0000 Reserved Reserved STCOMP STCOMP Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:16] Reserved reset value.

  • Page 617: I 2 C Serial Interface Controller (I 2 C)

    ISD94100 Series Technical Reference Manual 6.13 C Serial Interface Controller (I 6.13.1 Overview C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The ISD94100 series device provides two sets of I C controller which can function as either master or slave, provide multi-master capability, support up to 1Mbs transfer rate.

  • Page 618: Basic Configuration

    ISD94100 Series Technical Reference Manual APB Interface Wakeup Control Control Register I2Cn_SCL Bus Protocol I2Cn_SDA Interface Control Bus Clock Control I2Cn_SMBAL I2Cn_SMBSUS Management Control Note: n = 0 or 1 Figure 6.13-1 I C Controller Block Diagram 6.13.4 Basic Configuration 6.13.4.1 I2C0 Basic Configurations ...

  • Page 619: Functional Description

    ISD94100 Series Technical Reference Manual PC.14 MFP2 PD.1 MFP3 PD.9 MFP4 PD.15 MFP3 I2C0_SMBAL PA.12 MFP1 I2C0_SMBSUS PA.11 MFP1 6.13.4.2 I2C1 Basic Configurations  Clock source configuration – Enable I2C1 peripheral clock in I2C1CKEN (CLK_APBCLK0[9]).  Reset configuration – Reset I2C1 controller in I2C1RST (SYS_IPRST1[9]). ...

  • Page 620: Figure 6.13-2 I2C Bus Timing

    ISD94100 Series Technical Reference Manual line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP).

  • Page 621: Figure 6.13-4 Bit Transfer On The I C Bus

    ISD94100 Series Technical Reference Manual START (S) and Repeated START (Sr) conditions are functionally identical. By generating Repeated START (Sr) condition, a master can transmit and/or receive data from the same slave or different slaves without releasing the bus. 6.13.5.1.2 STOP signal I2C data flow follows the direction indicated by the R/W bit in addressing byte.

  • Page 622: Figure 6.13-6 Bit Transfer On The I C Bus

    ISD94100 Series Technical Reference Manual 6.13.5.1.3 Slave Address Transmission After a START (or Repeated START) condition, the master sends slave address to the SDA line. • In 7-bit address mode, one address byte is to be sent. – To enter Transmitter mode, a master sends the slave address with LSB reset (i.e. as 0). –...

  • Page 623: Figure 6.13-7 Acknowledge On The I C Bus

    ISD94100 Series Technical Reference Manual Clock pulse for acknowledgement SCL from master Data output by transmitter not acknowlegde Data output by receiver acknowlegde START condition Figure 6.13-7 Acknowledge on the I C Bus 6.13.5.1.5 Complete I2C Communication Flow The following figures illustrate how an I2C master initiates and completes a read/write operation with a 7-bit or 10-bit slave.

  • Page 624: Figure 6.13-10 Master Transmits Data To Slave By 10-Bit

    ISD94100 Series Technical Reference Manual one Read/Write bit – in this case it is ‘0’ indicating a write operation. The second address byte contains the lower 8-bit address. The master keeps sending data after addressing byte acknowledged. The 7-bit and 10-bit address devices can work on the same bus. ADDRESS 1st byte ADDRESS 2nd byte ‘0’...

  • Page 625: Figure 6.13-12 Control I

    ISD94100 Series Technical Reference Manual The code snippet below shows the I2C module initialization procedure: FMC->ISPCMD = FMC_ISPCMD_READ; // op code for 32-bit read is 0x00 CLK_EnableModuleClock(I2C0_MODULE); I2C_Open(I2C0, 100000); // set clock to 100K, and enable I2C_CTL_I2CEN_Msk in I2C_CTL I2C_SetSlaveAddr(I2C0, 0, 0x15, I2C_GCMODE_DISABLE); /* Slave Address : 0x15 */ …...
  • Page 626 ISD94100 Series Technical Reference Manual Sep 9, 2019 Page 626 of 928 Rev1.09...

  • Page 627: Figure 6.13-13 Master Transmitter Mode Control Flow

    ISD94100 Series Technical Reference Manual 6.13.5.2.2 Master Mode Figure 6.13-13 and Figure 6.13-14 illustrates the work flow as a Master Transmitter and a Master Receiver, respectively. Writing 1 to STA bit (I2C_CTL[5]) enters Master mode. This operation generates a START condition and therefore a new I2C session is started.
  • Page 628 ISD94100 Series Technical Reference Manual if (u32Status == 0x08) { /* START has been transmitted */ I2C_SET_DATA(I2C0, g_u8DeviceAddr << 1); /* Write SLA+W to Register I2CDAT */ I2C_SET_CONTROL_REG(I2C0, I2C_SI); /* Write 1 to SI to clear the I2C interrupt flag */ else if (u32Status == 0x18) { /* SLA+W has been transmitted and ACK has been received */ I2C_SET_DATA(I2C0, g_au8TxData[g_u8DataLen++]);...

  • Page 629: Figure 6.13-14 Master Receiver Mode Control Flow

    ISD94100 Series Technical Reference Manual STATUS=0x08 STATUS=0x40 STATUS=0x50 I2C_DAT I2C_DAT (SLA+R) (Data) (STA,STO,SI,AA)=(1,0,1,x) I2C_DAT=SLA+R (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(0,0,1,x) (Arbitration Lost) ACK STATUS=0x38 I2C_DAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x58 I2C_DAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x48 STATUS=0x08 (STA,STO,SI,AA)=(1,1,1,x) (Arbitration Lost) STATUS=0x38 STATUS=0xF8 I2C_DAT ACK/ (SLA+R) I2C_DAT=SLA+R (STA,STO,SI,AA)=(0,0,1,X) (STA,STO,SI,AA)=(0,1,1,x) (Arbitration Lost) ACK STATUS=0x10 STATUS= 0x68, 0x78, 0xB0...
  • Page 630 ISD94100 Series Technical Reference Manual g_u8DeviceAddr = slvaddr; I2C_SET_CONTROL_REG(I2C0, I2C_STA); /* again, generates START condition */ … /* ------- I2C interrupt service routine: I2C_MasterTx ------ */ /* see sample code for Figure 6.13-13 */ /* ------- I2C interrupt service routine: I2C_MasterRx ------ */ if (u32Status == 0x08) { /* START has been transmitted and prepare SLA+W */ I2C_SET_DATA(I2C0, (g_u8DeviceAddr <<...

  • Page 631: Figure 6.13-15 Slave Mode Control Flow

    ISD94100 Series Technical Reference Manual 6.13.5.2.3 Slave Mode After reset by default the ISD94100 device I C is not addressed and will not acknowledge the address on I C bus. Once the I2C address registers I2C_ADDRn (n=0~3) are written, and (STA, STO, SI, AA) = (0, 0, 1, 1), the ISD94100 I2C will acknowledge the matching address presented on I2C bus.
  • Page 632 ISD94100 Series Technical Reference Manual code will be 0xA0. User could follow the action for status code 0x88 as shown in the above figure when getting 0xA0 status. If I C is still transmitting data in addressed Slave mode but got a STOP or Repeat START, the status code will be 0xA0.
  • Page 633 ISD94100 Series Technical Reference Manual else if (u32Status == 0x88) { /* Previously addressed with own SLA address; NOT ACK has been returned */ g_u8DataLen = 0; I2C_SET_CONTROL_REG(I2C0, I2C_SI | I2C_AA); } else if (u32Status == 0xA0) { /* A STOP or repeated START has been received while still addressed as Slave/Receiver*/ g_u8DataLen = 0;...

  • Page 634: Figure 6.13-16 Gc Mode

    ISD94100 Series Technical Reference Manual 6.13.5.2.4 General Call (GC) Mode If the GC bit (I2C_ADDRn [0]) is set, the I C port hardware will respond to General Call address (00H). User can clear GC bit to disable general call function. When the GC bit is set and the I C in Slave mode, it can receive the general call address by 0x00 after master send general call address to I...
  • Page 635 ISD94100 Series Technical Reference Manual Note: After slave gets status of 0x98 and 0xA0, slave can switch to not address mode and own SLA will not be recognized. If entering this status, slave will not receive any I C signal or address from master.

  • Page 636: Figure 6.13-17 Arbitration Lost

    ISD94100 Series Technical Reference Manual 6.13.5.2.5 Multi-Master In some applications, there are two or more masters on the same I C bus to access slaves, and the masters may transmit data simultaneously. The I C supports multi-master by including collision detection and arbitration to prevent data corruption.

  • Page 637: Table 6.13.5-1 Reserved Smbus Address

    ISD94100 Series Technical Reference Manual 6.13.5.2.6 Bus Management (SMBus/PMBus Compatible) This section is relevant only when Bus Management feature is supported. Introduction The Bus Management is an I C interface through which various devices can communicate with each other and with the rest of the system. It is based on I C principles of operation.

  • Page 638: Figure 6.13-18 Bus Management Packet Protocol Diagram Element Key

    ISD94100 Series Technical Reference Manual Bus protocols There are eleven possible command protocols for any given device. A device may use any or all of the eleven protocols to communicate. The protocols are Quick Command, Send Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read Word, Process Call, Block Read, Block Write and Block Write-Block Read Process Call.

  • Page 639: Figure 6.13-19 7-Bit Addressable Device To Host Communication

    ISD94100 Series Technical Reference Manual To prevent message coming to the Bus Management host controller from unknown devices in unknown formats only one method of communication is allowed, a modified form of the Write Word protocol. The standard Write Word protocol is modified by replacing the command code with the alerting device’s address.

  • Page 640: Figure 6.13-21 Bus Management Alert Function

    ISD94100 Series Technical Reference Manual I2Cn_SMBAL I2C Controller Host Slave ARA Command Figure 6.13-21 Bus Management ALERT function Packet error checking A packet error checking mechanism has been introduced in the SMBus specification to improve reliability and communication robustness. Packet Error Checking is implemented by appending a Packet Error Code (PEC) at the end of each message transfer.

  • Page 641: Figure 6.13-22 Bus Management Time Out Timing

    ISD94100 Series Technical Reference Manual Start Stop Time-out SMBCLK (I2Cn_SCL) SMBDAT (I2Cn_SDA) Figure 6.13-22 Bus Management Time Out Timing Bus clock low time-out: In Master mode, the Master cumulative clock low extend time (T ) is detected LOW:MEXT In Slave mode, the slave cumulative clock low extend time (T ) is detected LOW:SEXT = CLKTO (I2C_CLKTOUT[7:0]) x 16x1024 (14-bit) x T...

  • Page 642: Table 6.13.5-2 Relationship Between I

    ISD94100 Series Technical Reference Manual This timing parameter covers the condition where a master has been dynamically added to the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In this case, the master must wait long enough to ensure that a transfer is not currently in progress. The peripheral supports a hardware bus idle detection.

  • Page 643: Figure 6.13-24 Setup Time Wrong Adjustment

    ISD94100 Series Technical Reference Manual Figure 6.13-24 Setup Time Wrong Adjustment For hold time wrong adjustment example, we use I C Baud Rate = 1200k and PCLK = 72 MHz, the SCL high/low duty = 60 PCLK. When we set HTCTL [5:0] (I2C_TMCTL[11:6]) to 61 and STCTL [5:0] (I2C_TMCTL[5:0]) to 0, then SDA output delay will over SCL high duty and cause bus error.

  • Page 644: Figure 6.13-26 I 2 C Data Shifting Direction

    ISD94100 Series Technical Reference Manual of shifting a byte. When I C is in a defined state and the serial interrupt flag (SI) is set, data in I2C_DAT [7:0] remains stable. While data is being shifted out, data on the bus is simultaneously being shifted in;...

  • Page 645: Table 6.13.5-3 I 2 C Status Code Description

    ISD94100 Series Technical Reference Manual Master Mode Slave Mode STATUS Description STATUS Description 0x08 Start 0xA0 Slave Transmit Repeat Start or Stop 0x10 Master Repeat Start 0xA8 Slave Transmit Address ACK 0x18 Master Transmit Address ACK 0xB8 Slave Transmit Data ACK 0x20 Master Transmit Address NACK 0xC0...

  • Page 646: Figure 6.13-27 I 2 C Time-Out Count Block Diagram

    ISD94100 Series Technical Reference Manual time-out counter. User may write 1 to clear TOIF to 0. Pclk 14-bits Counter Enable To I2C Interrupt Clear Counter DIV4 I2CEN INTEN Figure 6.13-27 I C Time-out Count Block Diagram 6.13.5.4.8 Wake-up Control Register (I2C_WKCTL) When chip enters Power-down mode and set WKEN (I2C_WKCTL [0]) to 1, other I C master can wake up our chip by addressing our I...

  • Page 647: Figure 6.13-28 I 2 C Wake-Up Related Signals Waveform

    ISD94100 Series Technical Reference Manual SCL(signal) PWD(signal) WKIF(I2C_WKSTS[0]) WRSTSWK(I2C_WKSTS[2]) WKACDONE(I2C_WKSTS[1]) SI(I2C_CTL[3]) Figure 6.13-28 I C Wake-Up Related Signals Waveform 6.13.5.4.10 The I C Control Register 1 (I2C_CTL1) If the enable 10-bit mode ADDR10EN (I2C_CTL1 [9]) is set, the I C will run in 10-bit mode. 6.13.5.4.11 The I C Status Register 1 (I2C_STATUS1)

  • Page 648: Figure 6.13-29 Eeprom Random Read

    ISD94100 Series Technical Reference Manual 6.13.5.4.15 C Bus Management Status Register (I2C_BUSSTS) Monitor PECDONE (I2C_BUSSTS[7]), BCDONE (I2C_BUSSTS[1]) PECERR (I2C_BUSSTS[2]) for PEC control flow. Monitor the SCTLDIN (I2C_BUSSTS[4]) for I2Cn_SMBSUS input status. 6.13.5.4.16 C Byte Number Register (I2C_PKTSIZE) When the PECEN bit (I2C_BUSCTL[1]) is set. The I C controller will calculate the PEC value of the data on the bus.

  • Page 649: Figure 6.13-30 Protocol Of Eeprom Random Read

    ISD94100 Series Technical Reference Manual STATUS=0x08 STATUS=0x18 I2C_DAT I2C_DAT (SLA+W) ROM Address High Byte I2C_DAT=ROM Address High Byte I2C_DAT=SLA+W STATUS=0xf8 (STA,STO,SI,AA)=(0,0,1,x) STATUS=0x20 (STA,STO,SI,AA)=(0,0,1,x) (STA,STO,SI,AA)=(1,0,1,x) (STA,STO,SI,AA)=(0,1,1,x) STATUS=0x28 STATUS=0x28 I2C_DAT ROM Address Low Byte I2C_DAT=ROM Address Low Byte (STA,STO,SI,AA)=(0,0,1,x) STATUS=0x30 STATUS=0xf8 (STA,STO,SI,AA)=(0,1,1,x) STATUS=0x58 STATUS=0xf8 STATUS=0x10...

  • Page 650: Register Map

    ISD94100 Series Technical Reference Manual 6.13.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value C Base Address: I2Cn_BA = 0x4008_0000 + (0x1000 *n) n= 0,1 I2C_CTL I2Cn_BA+0x00 R/W I C Control Register 0 0x0000_0000 I2C_ADDR0...
  • Page 651 ISD94100 Series Technical Reference Manual Any register not listed here is reserved and must not be written. The result of a read operation on these bits is undefined. The reserved register fields that listed in register description must be written to their reset value. Writing reserved fields with other than reset values may produce undefined results.

  • Page 652: Register Description

    ISD94100 Series Technical Reference Manual 6.13.7 Register Description I2C Control Register (I2C_CTL) Offset R/W Description Reset Value Register I2C_CTL I2Cn_BA+0x00 R/W I C Control Register 0 0x0000_0000 Reserved Reserved Reserved INTEN I2CEN Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:8] Reserved reset value.
  • Page 653 ISD94100 Series Technical Reference Manual When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter.
  • Page 654 ISD94100 Series Technical Reference Manual I2C Data Register (I2C_DAT) Offset R/W Description Reset Value Register I2C_DAT I2Cn_BA+0x08 R/W I C Data Register 0x0000_0000 Reserved Reserved Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:8] Reserved reset value.
  • Page 655 ISD94100 Series Technical Reference Manual I2C Status Register (I2C_STATUS) Offset R/W Description Reset Value Register I2C_STATUS I2Cn_BA+0x0C C Status Register 0 0x0000_00F8 Reserved Reserved Reserved STATUS Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:8] Reserved reset value.
  • Page 656 ISD94100 Series Technical Reference Manual I2C Clock Divided Register (I2C_CLKDIV) Offset R/W Description Reset Value Register I2C_CLKDIV I2Cn_BA+0x10 R/W I C Clock Divided Register 0x0000_0000 Reserved Reserved Reserved DIVIDER DIVIDER Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:10] Reserved reset value.
  • Page 657 ISD94100 Series Technical Reference Manual I2C Time-out Control Register (I2C_TOCTL) Offset R/W Description Reset Value Register I2C_TOCTL I2Cn_BA+0x14 R/W I C Time-out Control Register 0x0000_0000 Reserved Reserved Reserved Reserved TOCEN TOCDIV4 TOIF Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:3] Reserved reset value.
  • Page 658 ISD94100 Series Technical Reference Manual I2C Slave Address Register (ADDRx) Offset R/W Description Reset Value Register I2C_ADDR0 I2Cn_BA+0x04 R/W I C Slave Address Register0 0x0000_0000 I2C_ADDR1 I2Cn_BA+0x18 R/W I C Slave Address Register1 0x0000_0000 I2C_ADDR2 I2Cn_BA+0x1C R/W I C Slave Address Register2 0x0000_0000 I2C_ADDR3 I2Cn_BA+0x20...
  • Page 659 ISD94100 Series Technical Reference Manual I2C Slave Address Mask Register (ADDRMSKx) Offset R/W Description Reset Value Register I2C_ADDRMSK0 I2Cn_BA+0x24 R/W I C Slave Address Mask Register0 0x0000_0000 I2C_ADDRMSK1 I2Cn_BA+0x28 R/W I C Slave Address Mask Register1 0x0000_0000 I2C_ADDRMSK2 I2Cn_BA+0x2C R/W I C Slave Address Mask Register2 0x0000_0000 I2C_ADDRMSK3...
  • Page 660 ISD94100 Series Technical Reference Manual I2C Wake-up Control Register (I2C_WKCTL) Offset R/W Description Reset Value Register I2C_WKCTL I2Cn_BA+0x3C R/W I C Wake-up Control Register 0x0000_0000 Reserved Reserved Reserved NHDBUSEN Reserved WKEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:8] Reserved reset value.
  • Page 661 ISD94100 Series Technical Reference Manual I2C Wake-up Status Register (I2C_WKSTS) Offset R/W Description Reset Value Register I2C_WKSTS I2Cn_BA+0x40 R/W I C Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WRSTSWK WKAKDONE WKIF Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:3] Reserved reset value.
  • Page 662 ISD94100 Series Technical Reference Manual I2C Control Register 1 (I2C_CTL1) Offset R/W Description Reset Value Register I2C_CTL1 I2Cn_BA+0x44 R/W I C Control Register 1 0x0000_0000 Reserved Reserved Reserved ADDR10EN Reserved Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:10] Reserved reset value.
  • Page 663 ISD94100 Series Technical Reference Manual I2C Status Register 1 (I2C_STATUS1) Offset R/W Description Reset Value Register I2C_STATUS1 I2Cn_BA+0x48 R/W I C Status Register 1 0x0000_0000 Reserved Reserved Reserved ONBUSY Reserved ADMAT3 ADMAT2 ADMAT1 ADMAT0 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 664 ISD94100 Series Technical Reference Manual I2C Timing Configure Control Register (I2C_TMCTL) Offset R/W Description Reset Value Register I2C_TMCTL I2Cn_BA+0x4C R/W I C Timing Configure Control Register 0x0000_0000 Reserved HTCTL HTCTL Reserved STCTL STCTL Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:25] Reserved reset value.
  • Page 665 ISD94100 Series Technical Reference Manual I2C Bus Manage Control Register (I2C_BUSCTL) Offset R/W Description Reset Value Register I2C_BUSCTL I2Cn_BA+0x50 R/W I C Bus Management Control Register 0x0000_0000 Reserved Reserved Reserved PECDIEN BCDIEN ACKM9SI PECCLR TIDLE PECTXEN BUSEN SCTLOEN SCTLOSTS ALERTEN BMHEN BMDEN PECEN...
  • Page 666 ISD94100 Series Technical Reference Manual Packet Error Checking Byte Transmission/Reception 0 = No PEC transfer. PECTXEN 1 = PEC transmission is requested. Note: 1.This bit has no effect in slave mode when ACKMEN =0. BUS Enable Bit 0 = The system management function is Disabled. BUSEN 1 = The system management function is Enable.
  • Page 667 ISD94100 Series Technical Reference Manual I2C Bus Management Timer Control Register (I2C_BUSTCTL) Offset R/W Description Reset Value Register I2C_BUSTCTL I2Cn_BA+0x54 R/W I C Bus Management Timer Control Register 0x0000_0000 Reserved Reserved Reserved Reserved TORSTEN CLKTOIEN BUSTOIEN CLKTOEN BUSTOEN Description Bits Reserved.
  • Page 668 ISD94100 Series Technical Reference Manual I2C Bus Management Status Register (I2C_BUSSTS) Offset R/W Description Reset Value Register I2C_BUSSTS I2Cn_BA+0x58 R/W I C Bus Management Status Register 0x0000_0000 Reserved Reserved Reserved PECDONE CLKTO BUSTO SCTLDIN ALERT PECERR BCDONE BUSY Description Bits Reserved.
  • Page 669 ISD94100 Series Technical Reference Manual Note: 1. The I2Cn_SMBAL pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit. PEC Error in Reception 0 = Indicates the PEC value equal the received PEC data packet. PECERR 1 = Indicates the PEC value doesn’t match the receive PEC data packet.
  • Page 670 ISD94100 Series Technical Reference Manual I2C Byte Number Register (I2C_PKTSIZE) Offset R/W Description Reset Value Register I2C_PKTSIZE I2Cn_BA+0x5C R/W I C Packet Error Checking Byte Number Register 0x0000_0000 Reserved Reserved Reserved PLDSIZE PLDSIZE Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 671 ISD94100 Series Technical Reference Manual I2C PEC Value Register (I2C_PKTCRC) Offset R/W Description Reset Value Register I2C_PKTCRC I2Cn_BA+0x60 C Packet Error Checking Byte Value Register 0x0000_0000 Reserved Reserved Reserved PECCRC Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:8] Reserved reset value.
  • Page 672 ISD94100 Series Technical Reference Manual I2C Bus Management Timer Register (I2C_BUSTOUT) Offset R/W Description Reset Value Register I2C_BUSTOUT I2Cn_BA+0x64 R/W I C Bus Management Timer Register 0x0000_0005 Reserved Reserved Reserved BUSTO Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:8] Reserved reset value.
  • Page 673 ISD94100 Series Technical Reference Manual I2C Clock Low Timer Register (I2C_CLKTOUT) Offset R/W Description Reset Value Register I2C_CLKTOUT I2Cn_BA+0x68 R/W I C Bus Management Clock Low Timer Register 0x0000_0005 Reserved Reserved Reserved CLKTO Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:8] Reserved reset value.

  • Page 674: Serial Peripheral Interface (Spi)

    ISD94100 Series Technical Reference Manual 6.14 Serial Peripheral Interface (SPI) 6.14.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication interface. SPI devices communicate in full duplex mode using a master-slave architecture. The single master and the slave(s) communicate bi-directionally through a 4-wire interface. The ISD94100 series contains up to three sets of SPI controllers which perform serial-to-parallel conversion when receiving data from a peripheral device, and parallel-to-serial conversion when transmitting data to a peripheral device.

  • Page 675: Table 6.14.2-1 Spi Feature Difference (Spi0~Spi2)

    ISD94100 Series Technical Reference Manual SPI0 SPI1 / SPI2 Dual/Quad I/O Mode Two-Bit Transfer Mode SPI mode 8~16 bits data length: 8-level FIFO Depth 8-level Otherwise: 4-level Slave Time-out Function Slave 3-Wired Mode S Mode Table 6.14.2-1 SPI feature difference (SPI0~SPI2) Sep 9, 2019 Page 675 of 928 Rev1.09...

  • Page 676: Block Diagram

    ISD94100 Series Technical Reference Manual 6.14.3 Block Diagram SPI0_CLK Interface Control Core Logic SPI0_SS0 Peripheral clock SPI0_SS1 Status / Control Registers Interface SPI0_MOSI0 Control 4-Bit 8-Level TX TX Shift Skew SPI0_MOSI1 FIFO Buffer Register Buffer 4-Bit SPI0_MISO0 8-Level RX RX Shift Skew FIFO Buffer Register...
  • Page 677 ISD94100 Series Technical Reference Manual TX FIFO Buffer: The transmit FIFO buffer is a 4-/8-level depth, 32-bit wide, first-in, first-out register buffer. The data can be written to the transmit FIFO buffer in advance through software by writing the SPIn_TX register. In SPI mode for SPI1~SPI2, The transmit FIFO will be configured as 8-level while data length is set as 8~16 bits.

  • Page 678: Basic Configuration

    ISD94100 Series Technical Reference Manual 6.14.4 Basic Configuration 6.14.4.1 SPI0 Basic Configurations  Clock source configuration – Select the source of SPI0 peripheral clock on SPI0SEL (CLK_CLKSEL2[3:2]). – Enable SPI0 peripheral clock in SPI0CKEN (CLK_APBCLK0[12]).  Reset configuration – Reset SPI0 controller in SPI0RST (SYS_IPRST1[12]). ...
  • Page 679 ISD94100 Series Technical Reference Manual PD.4 MFP2 PC.1 MFP3 SPI1_MISO PD.3 MFP2 PC.0 MFP3 SPI1_MOSI PD.2 MFP2 PC.3 MFP3 SPI1_SS PD.5 MFP2 PC.4 MFP3 SPI1_I2SMCLK PD.6 MFP2 6.14.4.3 SPI2 Basic Configurations  Clock source configuration – Select the source of SPI0 peripheral clock on SPI2SEL (CLK_CLKSEL2[7:6]). –...

  • Page 680: Functional Description

    ISD94100 Series Technical Reference Manual SPIx_MOSI SPI master output or slave input pin S data output pin (I2Sx_DO) SPIx_I2SMCLK Not available S Master clock output pin Note: When using the I2S function in SPI1 and SPI2, please enable schmitt trigger function (Px_SMTEN) on corresponding pins.

  • Page 681: Figure 6.14-5 Spi0 Full-Duplex Master Mode Application Block Diagram

    ISD94100 Series Technical Reference Manual used to select the full-duplex or half-duplex in SPI transmission. The application block diagrams in Master and Slave mode are shown below. SPI_CLK SPI0_CLK SPI_DO SPI0_MISO0 I94100 Series Slave 0 SPI Master SPI_DI SPI0_MOSI0 SPI_SS SPI0_SS0 SPI0_SS1 SPI_CLK...

  • Page 682: Figure 6.14-7 Spi1 ~ Spi2 Full-Duplex Master Mode Application Block Diagram

    ISD94100 Series Technical Reference Manual SPIx_CLK SPI_CLK SPI_DO SPIx_MISO I94100 Series Slave SPI Master SPI_DI SPIx_MOSI SPI_SS SPIx_SS Note: x = 1, 2 Figure 6.14-7 SPI1 ~ SPI2 Full-Duplex Master Mode Application Block Diagram SPI_CLK SPIx_CLK SPI_DI SPIx_MISO I94100 Series Master SPI Slave SPI_DO...

  • Page 683: Figure 6.14-9 32-Bit In One Transaction

    ISD94100 Series Technical Reference Manual positive edge of SPI clock. Note: The settings of TXNEG and RXNEG are mutual exclusive. In other words, do not transmit and receive data at the same clock edge. Transmit/Receive Bit Length The bit length of a transaction word is defined in DWIDTH (SPIn_CTL[12:8]) and can be configured up to 32-bit length in a transaction word for transmitting and receiving.

  • Page 684: Figure 6.14-10 Automatic Slave Selection (Ssactpol = 0, Suspitv > 0X2)

    ISD94100 Series Technical Reference Manual SUSPITV (SPIn_CTL[7:4]) is greater than or equal to 3. In Master mode, if the value of SUSPITV is less than 3 and the AUTOSS is set as 1, the slave selection signal will be kept at active state between two successive transactions. If the AUTOSS bit is cleared, the slave selection output signal will be determined by the SS setting.

  • Page 685: Figure 6.14-11 Automatic Slave Selection (Ssactpol = 0, Suspitv < 0X3)

    ISD94100 Series Technical Reference Manual SS1 and SS (SPIn_SSCTL[1:0]) TXEMPTY (SPIn_STATUS[16]) SPIx_SSy pin One transaction One transaction SPIx_CLK pin The last transaction Note: n, x: Controller number (x = 0, 1, 2), y: Slave selection pin channel number in SPI0 (y = 0, 1) Figure 6.14-11 Automatic Slave Selection (SSACTPOL = 0, SUSPITV <...

  • Page 686: Figure 6.14-12 Byte Reorder Function

    ISD94100 Series Technical Reference Manual SPI_TX/SPI_RX TX/RX FIFO Buffer LSB = 0 (MSB first) MSB first MSB first & REORDER = 1 Byte3 Byte2 Byte1 Byte0 Byte0 Byte1 Byte2 Byte3 DWIDTH = 0 MSB first Byte0 Byte1 Byte2 DWIDTH = 24 MSB first Byte0 Byte1...

  • Page 687: Figure 6.14-14 Spi Half-Duplex Master Mode Application Block Diagram

    ISD94100 Series Technical Reference Manual SPIx_CLK SPI_CLK SPIx_MISOz I94120 Series Slave SPI Master SPI_DATA SPIx_MOSIz SPI_SS SPIx_SSy Note: x: Controller number (x = 0, 1, 2), y: Slave selection pin channel number in SPI0 (y = z: MOSI and MISO pin channel number in SPI0 (z = 0) Figure 6.14-14 SPI Half-Duplex Master Mode Application Block Diagram SPI_CLK SPIx_CLK...
  • Page 688 ISD94100 Series Technical Reference Manual 6.14.5.6 Slave 3-Wire Mode When SLV3WIRE (SPI0_SSCTL[4]) is set by software to enable the Slave 3-Wire mode, the SPI controller can work with no slave selection signal in Slave mode. The SLV3WIRE (SPI0_SSCTL[4]) only takes effect in Slave mode. Only three pins, SPI0_CLK, SPI0_MISO0, and SPI0_MOSI0, are required to communicate with a SPI master.

  • Page 689: Figure 6.14-16 Two-Bit Transfer Mode System Architecture

    ISD94100 Series Technical Reference Manual SPI0_CLK SPI_CLK SPI0_MISO0 SPI0_MISO[1:0] SPI_DO SPI0_MOSI0 SPI0_MOSI[1:0] SPI_DI SPI0_SS0/1 SPI_SS Slave 0 SPI0 Controller SPI_CLK Master SPI0_MISO1 SPI_DO SPI0_MOSI1 SPI_DI SPI_SS Slave 1 Figure 6.14-16 Two-Bit Transfer Mode System Architecture SPI0_SS0/1 pin SPI0_CLK pin SPI0_MOSI0 pin TX Data (n) TX Data (n+2) SPI0_MISO0 pin...

  • Page 690: Figure 6.14-18 Bit Sequence Of Dual Output Mode

    ISD94100 Series Technical Reference Manual The Dual I/O mode is not supported when the Slave 3-Wire mode or the Byte Reorder function is enabled. For Dual I/O mode, if both the DUALIOEN (SPI0_CTL[21]) and DATDIR (SPI0_CTL[20]) are set as 1, the SPI0_MOSI0 is the even bit data output and the SPI0_MISO0 will be set as the odd bit data output.

  • Page 691: Figure 6.14-20 Bit Sequence Of Quad Output Mode

    ISD94100 Series Technical Reference Manual 6.14.5.10 Quad I/O Mode The SPI0 controller also supports Quad I/O transfer when setting the QUADIOEN (SPI0_CTL[22]) to 1. Many general SPI flashes support Quad I/O transfer. The DATDIR bit (SPI0_CTL[20]) is used to define the direction of the transfer data. When the DATDIR (SPI0_CTL[20]) is set to 1, the controller will send the data to external device.

  • Page 692: Figure 6.14-21 Bit Sequence Of Quad Input Mode

    ISD94100 Series Technical Reference Manual SPI0_SS0/1 pin SPI0_CLK pin SPI0_MOSI0 pin 7 6 5 4 3 2 1 0 C 8 4 0 C 8 4 0 C 8 4 0 C 8 4 0 Master output Input Slave input SPI0_MISO0 pin D 9 5 1 D 9 5 1 D 9 5 1 D 9 5 1...

  • Page 693: Figure 6.14-22 Fifo Threshold Comparator

    ISD94100 Series Technical Reference Manual Valid Data Count in Transmit FIFO Buffer TXTHIF = 1 when A <= B TXTHIF = 0 when A > B Comparator TXTH Valid Data Count in Receive FIFO Buffer RXTHIF = 1 when C > D RXTHIF = 0 when C <= D Comparator RXTH...

  • Page 694: Figure 6.14-23 Transmit Fifo Buffer Example

    ISD94100 Series Technical Reference Manual TX Skew Buffer TX Shift Register Data 0 Data 0 Example 1 SPI0 H/W load TX H/W load Shift Write Register into DWIDTH =0 Buffer into 1 Data Shift Register Skew Buffer LSB = 1 TX Buffer Data 0 TXEMPTY = 1...

  • Page 695: Figure 6.14-24 Receive Fifo Buffer Example

    ISD94100 Series Technical Reference Manual RX Skew Buffer 1. H/W load Shift Register into RX …………….b0 …………..b32 RX Shift Register b31|b30...b1|b0 FIFO Example 1 H/W Load 2. H/W Load H/W Load 32 Skew Buffer SPI0 Skew Buffer into bits into RX FIFO Buffer into Shift DWIDTH =0...

  • Page 696: Figure 6.14-25 Tx Underflow Event And Slave Under Run Event

    ISD94100 Series Technical Reference Manual Figure 6.14-25 TX Underflow Event and Slave Under Run Event In 2-Bit Transfer mode, the transmit data is loaded into shift register after 2 datum have been written into the TX FIFO buffer. It uses two shift registers and two 4-level skew buffers concurrently. The detail timing of 2-Bit Transfer mode, please refer to the section of Two-Bit Transfer mode.

  • Page 697: Figure 6.14-28 Slave Mode Bit Count Error

    ISD94100 Series Technical Reference Manual Master mode reception operation. If the receive FIFO buffer contains 4 (or 8 for SPI0) unread data, the RXFULL (SPIn_STATUS[9]) will be set to 1 and the RXOVIF (SPIn_STATUS[11]) will be set to 1 if there is more serial data received from SPI0_MOSI0 and SPIx_MOSI (x=1, 2) pin and follow-up data will be dropped (refer to the Receive FIFO Buffer Example figure).
  • Page 698 ISD94100 Series Technical Reference Manual A receive time-out function is built-in in this controller. When the receive FIFO is not empty and no read operation in receive FIFO over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode, the receive time-out occurs and the RXTOIF (SPIn_STATUS[12]) will be set to 1.
  • Page 699 ISD94100 Series Technical Reference Manual Note: If underflow event occurs in SPI Slave mode, there are two conditions which make SPI Slave mode return to idle state and then goes for next transfer: (1) set TXRST to 1 (2) slave select signal is changed to inactive state.

  • Page 700: Figure 6.14-30 I 2 S Data Format Timing Diagram

    ISD94100 Series Technical Reference Manual Note that when using the I2S function in SPI1 and SPI2, please enable schmitt trigger function (Px_SMTEN) on corresponding pins. I2Sx_BCLK I2Sx_LRCLK I2Sx_DI / I2Sx_DO word N-1 word N word N+1 right channel left channel right channel Note: x: Controller number (x = 1, 2)

  • Page 701: Figure 6.14-31 Msb Justified Data Format Timing Diagram

    ISD94100 Series Technical Reference Manual In MSB justified data format, the MSB is sent and latched on the first clock of an audio channel. I2Sx_BCLK I2Sx_LRCLK I2Sx_DI / I2Sx_DO word N-1 word N word N+1 right channel left channel right channel Note: x: Controller number (x = 1, 2) Figure 6.14-31 MSB Justified Data Format Timing Diagram...
  • Page 702 ISD94100 Series Technical Reference Manual Sep 9, 2019 Page 702 of 928 Rev1.09...
  • Page 703 ISD94100 Series Technical Reference Manual 6.14.5.14 I S Mode FIFO operation Mono 8-bit data mode SPIn_I2SCTL Stereo 8-bit data mode, ORDER ( [7]) = 0 LEFT+1 RIGHT+1 LEFT RIGHT SPIn_I2SCTL Stereo 8-bit data mode, ORDER ( [7]) = 1 RIGHT+1 LEFT+1 RIGHT LEFT...

  • Page 704: Timing Diagram

    ISD94100 Series Technical Reference Manual Figure 6.14-34 FIFO Contents for Various I S Modes 6.14.6 Timing Diagram The active state of slave selection signal can be defined by setting the SSACTPOL (SPIn_SSCTL[2]). The SPI clock which is in idle state can be configured as high or low state by setting the CLKPOL (SPIn_CTL[3]).

  • Page 705: Figure 6.14-36 Spi Timing In Master Mode (Alternate Phase Of Spix_Clk)

    ISD94100 Series Technical Reference Manual Figure 6.14-36 SPI Timing in Master Mode (Alternate Phase of SPIx_CLK) SSACTPOL=1 SPIx_SSy pin SSACTPOL=0 CLKPOL=0 SPIx_CLK pin CLKPOL=1 SPIx_MISOz pin TX[6] TX[0] TX[7] TX[6] TX[7] TX[0] SPIx_MOSIz pin RX[6] RX[0] RX[7] RX[6] RX[7] RX[0] Note: Slave Mode Registers Setting: SLAVE=1, LSB=0, DWIDTH=0x08...

  • Page 706: Programming Examples

    ISD94100 Series Technical Reference Manual 6.14.7 Programming Examples Example 1: The SPI controller is set as a full-duplex master to access an off-chip slave device with the following specifications:  Data bit is latched on positive edge of SPI bus clock. ...
  • Page 707 ISD94100 Series Technical Reference Manual  Data bit is latched on positive edge of SPI bus clock.  Data bit is driven on negative edge of SPI bus clock.  Data is transferred from LSB first.  SPI bus clock is idle at high state. ...

  • Page 708: Register Map

    ISD94100 Series Technical Reference Manual 6.14.8 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value SPI Base Address: SPI0_BA = 0x4006_0000 SPI1_BA = 0x4006_1000 SPI2_BA = 0x4006_2000 SPI0_CTL SPI0_BA+0x00 R/W SPI0 Control Register 0x0000_0034 SPI0_CLKDIV SPI0_BA+0x04...
  • Page 709 ISD94100 Series Technical Reference Manual Register Offset R/W Description Reset Value SPI Base Address: SPI0_BA = 0x4006_0000 SPI1_BA = 0x4006_1000 SPI2_BA = 0x4006_2000 SPI2_I2SSTS SPI2_BA+0x68 R/W SPI2 I2S Status Register 0x0005_0100 Note: Any register not listed here is reserved and must not be written. The result of a read operation on these bits is undefined. The reserved register fields that listed in register description must be written to their reset value.

  • Page 710: Register Description

    ISD94100 Series Technical Reference Manual 6.14.9 Register Description SPI Control Register (SPI0_CTL) Register Offset R/W Description Reset Value SPI0_CTL SPI0_BA+0x00 R/W SPI0 Control Register 0x0000_0034 Reserved Reserved QUADIOEN DUALIOEN DATDIR REORDER SLAVE UNITIEN TWOBIT RXONLY HALFDPX DWIDTH SUSPITV CLKPOL TXNEG RXNEG SPIEN Description...
  • Page 711 ISD94100 Series Technical Reference Manual 1 = SPI unit transfer interrupt Enabled. 2-bit Transfer Mode Enable Bit (Only Supported in SPI0) 0 = 2-Bit Transfer mode Disabled. 1 = 2-Bit Transfer mode Enabled. [16] TWOBIT Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2 serial transmitted bit data is from the second FIFO buffer data.
  • Page 712 ISD94100 Series Technical Reference Manual Transmit on Negative Edge TXNEG 0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. 1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. Receive on Negative Edge RXNEG 0 = Received data input signal is latched on the rising edge of SPI bus clock.
  • Page 713 ISD94100 Series Technical Reference Manual SPI Clock Divider Register (SPI0_CLKDIV) Register Offset R/W Description Reset Value SPI0_CLKDIV SPI0_BA+0x04 R/W SPI0 Clock Divider Register 0x0000_0000 Reserved Reserved Reserved DIVIDER DIVIDER Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 714 ISD94100 Series Technical Reference Manual SPI Slave Select Control Register (SPI0_SSCTL) Register Offset R/W Description Reset Value SPI0_SSCTL SPI0_BA+0x08 R/W SPI0 Slave Select Control Register 0x0000_0000 SLVTOCNT SLVTOCNT Reserved SSINAIEN SSACTIEN Reserved SLVURIEN SLVBEIEN Reserved SLVTORST SLVTOIEN SLV3WIRE AUTOSS SSACTPOL Description Bits Slave Mode Time-out Period (Only Supported in SPI0)
  • Page 715 ISD94100 Series Technical Reference Manual Slave Mode Time-out Interrupt Enable Bit (Only Supported in SPI0) SLVTOIEN 0 = Slave mode time-out interrupt Disabled. 1 = Slave mode time-out interrupt Enabled. Slave 3-wire Mode Enable Bit (Only Supported in SPI0) Slave 3-wire mode is only available in SPI0. In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO and SPI0_MOSI pins.
  • Page 716 ISD94100 Series Technical Reference Manual SPI PDMA Control Register (SPI0_PDMACTL) Register Offset R/W Description Reset Value SPI0_PDMACTL SPI0_BA+0x0C R/W SPI0 PDMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDMARST RXPDMAEN TXPDMAEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write [31:3] Reserved with reset value.
  • Page 717 ISD94100 Series Technical Reference Manual SPI FIFO Control Register (SPI0_FIFOCTL) Register Offset R/W Description Reset Value SPI0_FIFOCTL SPI0_BA+0x10 R/W SPI0 FIFO Control Register 0x4400_0000 Reserved TXTH Reserved RXTH Reserved Reserved TXFBCLR RXFBCLR TXUFIEN TXUFPOL RXOVIEN RXTOIEN TXTHIEN RXTHIEN TXRST RXRST Description Bits Reserved.
  • Page 718 ISD94100 Series Technical Reference Manual 1 = Slave TX underflow interrupt Enabled. TX Underflow Data Polarity 0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. 1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. TXUFPOL Note1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
  • Page 719 ISD94100 Series Technical Reference Manual SPI Status Register (SPI0_STATUS) Register Offset R/W Description Reset Value SPI0_STATUS SPI0_BA+0x14 R/W SPI0 Status Register 0x0005_0110 TXCNT RXCNT TXRXRST Reserved TXUFIF TXTHIF TXFULL TXEMPTY SPIENSTS Reserved RXTOIF RXOVIF RXTHIF RXFULL RXEMPTY SLVURIF SLVBEIF SLVTOIF SSLINE SSINAIF SSACTIF...
  • Page 720 ISD94100 Series Technical Reference Manual 1 = Transmit FIFO buffer is full. Transmit FIFO Buffer Empty Indicator (Read Only) [16] TXEMPTY 0 = Transmit FIFO buffer is not empty. 1 = Transmit FIFO buffer is empty. SPI Enable Status (Read Only) 0 = The SPI controller is disabled.
  • Page 721 ISD94100 Series Technical Reference Manual Slave Time-out Interrupt Flag (Only Supported in SPI0) When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI0_SSCTL[31:16]) SLVTOIF before one transaction is done, the slave time-out interrupt event will be asserted.
  • Page 722 ISD94100 Series Technical Reference Manual SPI Data Transmit Register (SPI0_TX) Register Offset R/W Description Reset Value SPI0_TX SPI0_BA+0x20 SPI0 Data Transmit Register 0x0000_0000 Description Bits Data Transmit Register The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers.
  • Page 723 ISD94100 Series Technical Reference Manual SPI Data Receive Register (SPI0_RX) Register Offset R/W Description Reset Value SPI0_RX SPI0_BA+0x30 SPI0 Data Receive Register 0x0000_0000 Description Bits Data Receive Register There are 8-level FIFO buffers in this controller. The data receive register holds the data [31:0] received from SPI data input pin.
  • Page 724 ISD94100 Series Technical Reference Manual SPI Control Register (SPIn_CTL) Register Offset R/W Description Reset Value SPI1_CTL SPI1_BA+0x00 R/W SPI1 Control Register 0x0000_0034 SPI2_CTL SPI2_BA+0x00 R/W SPI2 Control Register 0x0000_0034 Note: Not supported in I S mode. Reserved DATDIR REORDER SLAVE UNITIEN Reserved Reserved...
  • Page 725 ISD94100 Series Technical Reference Manual SPI Half-duplex Transfer Enable Bit This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIn_CTL[20]) can be used to set the data direction in half-duplex transfer. [14] HALFDPX 0 = SPI operates in full-duplex transfer.
  • Page 726 ISD94100 Series Technical Reference Manual SPI Transfer Control Enable Bit In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1. 0 = Transfer control Disabled.
  • Page 727 ISD94100 Series Technical Reference Manual SPI Clock Divider Register (SPIn_CLKDIV) Register Offset R/W Description Reset Value SPI1_CLKDIV SPI1_BA+0x04 R/W SPI1 Clock Divider Register 0x0000_0000 SPI2_CLKDIV SPI2_BA+0x04 R/W SPI2 Clock Divider Register 0x0000_0000 Reserved Reserved Reserved DIVIDER DIVIDER Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 728 ISD94100 Series Technical Reference Manual SPI Slave Select Control Register (SPIn_SSCTL) Register Offset R/W Description Reset Value SPI1_SSCTL SPI1_BA+0x08 R/W SPI1 Slave Select Control Register 0x0000_0000 SPI2_SSCTL SPI2_BA+0x08 R/W SPI2 Slave Select Control Register 0x0000_0000 Reserved Reserved Reserved SSINAIEN SSACTIEN Reserved SLVURIEN SLVBEIEN...
  • Page 729 ISD94100 Series Technical Reference Manual 1 = The slave selection signal is active high. Reserved. Any values read should be ignored. When writing to this field always write with Reserved reset value. Slave Selection Control (Master Only) If AUTOSS bit is cleared to 0, 0 = Set the SPIn_SS line to inactive state.
  • Page 730 ISD94100 Series Technical Reference Manual SPI PDMA Control Register (SPIn_PDMACTL) Register Offset R/W Description Reset Value SPI1_PDMACTL SPI1_BA+0x0C R/W SPI1 PDMA Control Register 0x0000_0000 SPI2_PDMACTL SPI2_BA+0x0C R/W SPI2 PDMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDMARST RXPDMAEN TXPDMAEN Description Bits Reserved.
  • Page 731 ISD94100 Series Technical Reference Manual SPI FIFO Control Register (SPIn_FIFOCTL) Register Offset R/W Description Reset Value SPI1_FIFOCTL SPI1_BA+0x10 R/W SPI1 FIFO Control Register 0x2200_0000 SPI2_FIFOCTL SPI2_BA+0x10 R/W SPI2 FIFO Control Register 0x2200_0000 Reserved TXTH Reserved RXTH Reserved Reserved TXFBCLR RXFBCLR TXUFIEN TXUFPOL RXOVIEN...
  • Page 732 ISD94100 Series Technical Reference Manual TX Underflow Interrupt Enable Bit When TX underflow event occurs in Slave mode, TXUFIF (SPIn_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt. TXUFIEN 0 = Slave TX underflow interrupt Disabled. 1 = Slave TX underflow interrupt Enabled.
  • Page 733 ISD94100 Series Technical Reference Manual SPI Status Register (SPIn_STATUS) Register Offset R/W Description Reset Value SPI1_STATUS SPI1_BA+0x14 R/W SPI1 Status Register 0x0005_0110 SPI2_STATUS SPI2_BA+0x14 R/W SPI2 Status Register 0x0005_0110 Note: Not supported in I S mode. TXCNT RXCNT TXRXRST Reserved TXUFIF TXTHIF TXFULL...
  • Page 734 ISD94100 Series Technical Reference Manual Transmit FIFO Buffer Full Indicator (Read Only) TXFULL [17] 0 = Transmit FIFO buffer is not full. 1 = Transmit FIFO buffer is full. Transmit FIFO Buffer Empty Indicator (Read Only) [16] TXEMPTY 0 = Transmit FIFO buffer is not empty. 1 = Transmit FIFO buffer is empty.
  • Page 735 ISD94100 Series Technical Reference Manual 1 = Slave mode bit count error event occurs. Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. Reserved.
  • Page 736 ISD94100 Series Technical Reference Manual SPI Data Transmit Register (SPIn_TX) Register Offset R/W Description Reset Value SPI1_TX SPI1_BA+0x20 SPI1 Data Transmit Register 0x0000_0000 SPI2_TX SPI2_BA+0x20 SPI2 Data Transmit Register 0x0000_0000 Description Bits Data Transmit Register The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
  • Page 737 ISD94100 Series Technical Reference Manual SPI Data Receive Register (SPIn_RX) Register Offset R/W Description Reset Value SPI1_RX SPI1_BA+0x30 SPI1 Data Receive Register 0x0000_0000 SPI2_RX SPI2_BA+0x30 SPI2 Data Receive Register 0x0000_0000 Bits Description Data Receive Register There are 4-level FIFO buffers in this controller. The data receive register holds the data [31:0] received from SPI data input pin.
  • Page 738 ISD94100 Series Technical Reference Manual I2S Control Register (SPIn_I2SCTL) Register Offset R/W Description Reset Value SPI1_I2SCTL SPI1_BA+0x60 R/W SP1 I2S Control Register 0x0000_0000 SPI2_I2SCTL SPI2_BA+0x60 R/W SPI2 I2S Control Register 0x0000_0000 Note: Not supported in SPI mode. Reserved FORMAT Reserved LZCIEN RZCIEN RXLCH...
  • Page 739 ISD94100 Series Technical Reference Manual Force Left Channel Zero Cross Data Option Bit If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIn_I2SSTS register is set to 1 and left channel data will force zero. This function is only available in transmit operation.
  • Page 740 ISD94100 Series Technical Reference Manual S Controller Enable Bit 0 = Disabled I S mode. 1 = Enabled I S mode. Note: I2SEN 1. If enable this bit, I2Sx_BCLK will start to output in Master mode. 2. Before changing the configurations of SPIn_I2SCTL, SPIn_I2SCLK, and SPIn_FIFOCTL registers, user shall clear the I2SEN (SPIn_I2SCTL[0]) and confirm the I2SENSTS (SPIn_I2SSTS[15]) is 0.
  • Page 741 ISD94100 Series Technical Reference Manual I2S Clock Divider Control Register (SPIn_I2SCLK) Register Offset R/W Description Reset Value SPI1_I2SCLK SPI1_BA+0x64 R/W SPI1 I S Clock Divider Control Register 0x0000_0000 SPI2_I2SCLK SPI2_BA+0x64 R/W SPI2 I S Clock Divider Control Register 0x0000_0000 Note: Not supported in SPI mode. Reserved Reserved BCLKDIV...
  • Page 742 ISD94100 Series Technical Reference Manual Master Clock Divider If MCLKEN is set to 1, I S controller will generate master clock for external audio devices. The frequency of master clock, f , is determined by the following expressions: MCLK clock If MCLKDIV >= 1,.
  • Page 743 ISD94100 Series Technical Reference Manual I2S Status Register (SPIn_I2SSTS) Register Offset R/W Description Reset Value SPI1_I2SSTS SPI1_BA+0x68 R/W SPI1 I S Status Register 0x0005_0100 SPI2_I2SSTS SPI2_BA+0x68 R/W SPI2 I S Status Register 0x0005_0100 Note: Not supported in SPI mode. Reserved TXCNT Reserved RXCNT...
  • Page 744 ISD94100 Series Technical Reference Manual Note: This bit will be cleared by writing 1 to it. Transmit FIFO Threshold Interrupt Flag (Read Only) 0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
  • Page 745 ISD94100 Series Technical Reference Manual Right Channel (Read Only) This bit indicates the current transmit data is belong to which channel. RIGHT 0 = Left channel. 1 = Right channel. Reserved. Any values read should be ignored. When writing to this field always write with [3:0] Reserved reset value.

  • Page 746: Crc Controller (Crc)

    ISD94100 Series Technical Reference Manual 6.15 CRC Controller (CRC) 6.15.1 Overview The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with programmable polynomial settings. 6.15.2 Features  Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32  CRC-CCITT: X ...

  • Page 747: Block Diagram

    ISD94100 Series Technical Reference Manual 6.15.3 Block Diagram Checksum CRC CTL CRC Seed CCITT Checksum Reverse / Byte 3 CRC-8 1's COMP Byte 2 In Data Bit Reverse / Byte 1 1's COMP Byte 0 CRC-16 CRC-32 CRC Control Unit Figure 6.15-1 CRC Generator Block Diagram 6.15.4 Basic Configuration ...

  • Page 748: Figure 6.15-2 Checksum Bit Order Reverse Functional Block

    ISD94100 Series Technical Reference Manual (CRC_CTL[24] Write Data Bit Order Reverse). The functional block is also shown in Figure 6.15-3. Perform CHKSINIT (CRC_CTL[1])] Checksum Initialization) to load the initial checksum value from CRC_SEED register value Write data to CRC_DAT register to calculate CRC checksum. Get the CRC checksum result by reading CRC_CHECKSUM register.

  • Page 749: Register Map

    ISD94100 Series Technical Reference Manual 6.15.6 Register Map R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register CRC Base Address: CRC_BA= 0x4003_1000 CRC_CTL CRC_BA+0x00 R/W CRC Control Register 0x2000_0000 CRC_DAT CRC_BA+0x04 R/W CRC Write Data Register 0x0000_0000 CRC_SEED CRC_BA+0x08...

  • Page 750: Register Description

    ISD94100 Series Technical Reference Manual 6.15.7 Register Description CRC Control Register (CRC_CTL) Offset R/W Description Reset Value Register CRC_CTL CRC_BA+0x00 R/W CRC Control Register 0x2000_0000 CRCMODE DATLEN CHKSFMT DATFMT CHKSREV DATREV Reserved Reserved Reserved CHKSINIT CRCEN Description Bits CRC Polynomial Mode This field indicates the CRC operation polynomial mode.
  • Page 751 ISD94100 Series Technical Reference Manual Checksum Bit Order Reverse This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register. [25] CHKSREV 0 = Bit order reverse for CRC checksum Disabled. 1 = Bit order reverse for CRC checksum Enabled. Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
  • Page 752 ISD94100 Series Technical Reference Manual CRC Write Data Register (CRC_DAT) Offset R/W Description Reset Value Register CRC_DAT CRC_BA+0x04 R/W CRC Write Data Register 0x0000_0000 DATA DATA DATA DATA Description Bits CRC Write Data Bits User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
  • Page 753 ISD94100 Series Technical Reference Manual CRC Seed Register (CRC_SEED) Offset R/W Description Reset Value Register CRC_SEED CRC_BA+0x08 R/W CRC Seed Register 0xFFFF_FFFF SEED SEED SEED SEED Description Bits CRC Seed Value This field indicates the CRC seed value. [31:0] SEED Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
  • Page 754 ISD94100 Series Technical Reference Manual CRC Checksum Register (CRC_CHECKSUM) Offset R/W Description Reset Value Register CRC_CHECKSUM CRC_BA+0x0C CRC Checksum Register 0xFFFF_FFFF CHECKSUM CHECKSUM CHECKSUM CHECKSUM Description Bits CRC Checksum Results [31:0] CHECKSUM This field indicates the CRC checksum result. Sep 9, 2019 Page 754 of 928 Rev1.09...

  • Page 755: Enhanced 12-Bit Analog-To-Digital Converter (Eadc)

    ISD94100 Series Technical Reference Manual 6.16 Enhanced 12-bit Analog-to-Digital Converter (EADC) 6.16.1 Overview The ISD94100 series contains one 12-bit successive approximation analog-to-digital converter (SAR ADC converter) with 13 external input channels. The ADC converter can be started by software trigger, PWM0 triggers, timer0~3 overflow pulse triggers, ADINT0, ADINT1 interrupt EOC (End of conversion) pulse trigger and external pin (EADC0_ST) input signal.

  • Page 756: Block Diagram

    ISD94100 Series Technical Reference Manual 6.16.3 Block Diagram Analog Macro 12-bit DAC Analog Control Logics Comparator Successive EADC0_CH0 Approximations Register EADC0_CH12 Sample and Hold A/D result [11:0] CHSEL (EADC_SCTLn[4:0]) A/D Sample Module 12 Digatal Control Logics A/D Sample Module 0 &...

  • Page 757: Functional Description

    ISD94100 Series Technical Reference Manual EADC0_CH2 PA.2 MFP2 EADC0_CH3 PA.3 MFP2 EADC0_CH4 PA.4 MFP2 EADC0_CH5 PA.5 MFP2 EADC0_CH6 PA.6 MFP2 EADC0_CH7 PA.7 MFP2 EADC0_CH8 PA.8 MFP2 EADC0_CH9 PA.9 MFP2 EADC0_CH10 PD.13 MFP2 EADC0_CH11 PD.14 MFP2 EADC0_CH12 PD.15 MFP2 PA.10 MFP2 EADC0_ST PD.10 MFP2...

  • Page 758: Figure 6.16-2 Sample Module 0~3 Block Diagram

    ISD94100 Series Technical Reference Manual Sample Module EXTREN (EADC_SCTL0[4]) Sample Module EADC0_ST pin signal EXTFEN (EADC_SCTL0[5]) Disable hardware Trigger ADINT0 interrupt EOC pulse ADINT1 interrupt EOC pulse Timer0 overflow pulse Timer1 overflow pulse Timer2 overflow pulse Timer3 overflow pulse reset PWM0TG0 PWM0TG1 EOC0...

  • Page 759: Figure 6.16-3 Sample Module 4~12 Block Diagram

    ISD94100 Series Technical Reference Manual Sample Module EXTREN (EADC_SCTL4[4]) Sample Module EADC0_ST pin signal EXTFEN (EADC_SCTL4[5]) Disable hardware Trigger ADINT0 interrupt EOC pulse ADINT1 interrupt EOC pulse Timer0 overflow pulse Timer1 overflow pulse Timer2 overflow pulse Timer3 overflow pulse reset PWM0TG0 PWM0TG1 EOC4...

  • Page 760: Figure 6.16-4 Eadc Clock Control

    ISD94100 Series Technical Reference Manual EADCCKEN (CLK_APBCLK0[28]) EADC PCLK1 1/(EADCDIV+1) EADCDIV (CLK_CLKDIV0[23:16]) Figure 6.16-4 EADC Clock Control 6.16.5.2 ADC Software Trigger Mode When a ADC conversion is performed on the sample module specified single channel, the operations are as follows: 1.

  • Page 761: Figure 6.16-6 Sample Module Conversion Priority Arbitrator Diagram

    ISD94100 Series Technical Reference Manual Note: If the interval between next conversion is more than 100 us, ADC would enter idle state automatically. User needs to execute a dummy conversion before normal operation. In other words, the first conversion result is incorrect when ADC is in idle state. 6.16.5.3 ADC Conversion Priority There is a priority group converter for determining the conversion order when multiple sample module trigger flags are set at the same time.

  • Page 762: Table 6.16.5-1 The Relation Between Resolution And Conversion Cycles

    ISD94100 Series Technical Reference Manual 6.16.5.4 Conversion Cycles and Sampling Rate Frequency There are four kinds of resolution which could be configured by RESSEL (EADC_CTL[7:6]). Each resolution corresponds to different conversion cycles. The relation is as Table 6.16.5-1. Resolution Minimum Conversion Cycles 6 bit 8 ADC_CLK 8 bit...

  • Page 763: Figure 6.16-7 Specific Sample Module Adc Eoc Signal For Adint0~3 Interrupt

    ISD94100 Series Technical Reference Manual 2. Set software trigger SWTRG2 (EADC_SWTRG[2]) to 1 to start a sample module 2 ADC conversion, after the conversion completes, it generates an EOC2 pulse signal and ADINT0 interrupt pulse at end of sample module 2 ADC conversion, ADINT0 interrupt pulse will trigger the sample module 0, 1, 2 to start the ADC conversions.

  • Page 764: Figure 6.16-8 Pwm-Triggered Adc Start Conversion

    ISD94100 Series Technical Reference Manual Delay time Delay Delay Starts A/D time time Starts A/D Starts A/D converting converting converting Synchronized with PWM Synchronized with PWM Synchronized with PWM central point (centre-aligned rising edge falling edge mode only) Figure 6.16-8 PWM-triggered ADC Start Conversion The Figure 6.16-9 shows the programmable delay time for other trigger source.

  • Page 765: Figure 6.16-10 Conversion Start Delay Timing Diagram

    ISD94100 Series Technical Reference Manual A/D conversion start delay time (Td) A/D conversion time PCLK Synchronous to ADC clock delay 1 ADC clock up to 1 ADC clock PWRITE SWTRGn (EADC_SWTRG[n], n=0~12) ADC start First ADC clock ADC Status Sampling Idle state Hold ADIFn...

  • Page 766: Figure 6.16-11 Eadc0_St De-Bounce Timing Diagram

    ISD94100 Series Technical Reference Manual PCLK 2 PCLK 3 PCLK 2 PCLK 3 PCLK EADC0_ST EADC0_ST falling detect EADC0_ST rising detect Figure 6.16-11 EADC0_ST De-bounce Timing Diagram 6.16.5.10 ADC Extend Sampling Time When ADC operation at high ADC clock rate, the sampling time of analog input voltage may not enough if the analog channel has heavy loading to cause fully charge time is longer.

  • Page 767: Figure 6.16-12 Adc Extend Sampling Timing Diagram

    ISD94100 Series Technical Reference Manual Figure 6.16-12 ADC Extend Sampling Timing Diagram 6.16.5.11 Conversion Result Monitor by Compare Mode The ADC controller provides four sets of compare registers EADC_CMP0 ~ EADC_CMP3 to monitor a maximum of four specified sample module 0~12 conversion results from ADC conversion module, as shown in the Figure 6.16-13.

  • Page 768: Figure 6.16-14 Adc Controller Interrupts

    ISD94100 Series Technical Reference Manual register is a shadow register of highest priority EADC_DAT register. The lower number sample module is higher priority. After PDMA read EADC_CURDAT register, the VAILD of the shadow EADC_DAT register will be automatically cleared. 6.16.5.14 Interrupt Sources The ADC converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion or the end of conversion decide by INTPOS (EADC_SCTLn[22], n=0~12).

  • Page 769: Figure 6.16-15 Adc Start Up Sequence With Calibration

    ISD94100 Series Technical Reference Manual Table 6.16.5-2 EADC Power Saving Mode When EADC is activated by setting ADCEN(EADC_CTL[0]) to 1, the startup sequence will execute automatically. After start up sequence finished, PWUPRDY (EADC_PWRM[0]) will be set to 1 by HW which means ready to convert. ADCEN (EADC_CTL[0]) must be kept at 1 until PWUPRDY (EADC_PWRM[0]) is set to 1 during the startup sequence.

  • Page 770: Figure 6.16-16 Model Of The Sampling Network

    ISD94100 Series Technical Reference Manual EADC Figure 6.16-16 Model of the sampling network (kohm) Minimum sampling time (ns) 0.05 1256 3083 6193 Table 6.16.5-3 EADC minimum sampling time Sep 9, 2019 Page 770 of 928 Rev1.09...

  • Page 771: Register Map

    ISD94100 Series Technical Reference Manual 6.16.6 Register Map R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register EADC Base Address: EADC_BA = 0x4004_3000 EADC_DAT0 EADC_BA+0x00 ADC Data Register 0 for Sample Module 0 0x0000_0000 EADC_DAT1 EADC_BA+0x04...
  • Page 772 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register EADC Base Address: EADC_BA = 0x4004_3000 EADC_SCTL7 EADC_BA+0x9C R/W ADC Sample Module 7 Control Register 0x0000_0000 EADC_SCTL8 EADC_BA+0xA0 R/W ADC Sample Module 8 Control Register 0x0000_0000 EADC_SCTL9 EADC_BA+0xA4 R/W ADC Sample Module 9 Control Register 0x0000_0000 EADC_SCTL10 EADC_BA+0xA8...
  • Page 773 ISD94100 Series Technical Reference Manual The reserved register fields that listed in register description must be written to their reset value. Writing reserved fields with other than reset values may produce undefined results. Sep 9, 2019 Page 773 of 928 Rev1.09...

  • Page 774: Register Description

    ISD94100 Series Technical Reference Manual 6.16.7 Register Description ADC Data Registers (EADC_DAT0~ EADC_DAT12) Offset R/W Description Reset Value Register EADC_DAT0 EADC_BA+0x00 ADC Data Register 0 for Sample Module 0 0x0000_0000 EADC_DAT1 EADC_BA+0x04 ADC Data Register 1 for Sample Module 1 0x0000_0000 EADC_DAT2 EADC_BA+0x08...
  • Page 775 ISD94100 Series Technical Reference Manual Overrun Flag If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. [16] 0 = Data in RESULT[11:0] is recent conversion result. 1 = Data in RESULT[11:0] is overwrite.
  • Page 776 ISD94100 Series Technical Reference Manual ADC PDMA Current Transfer Data Register (EADC_CURDAT) Offset R/W Description Reset Value Register EADC_CURDAT EADC_BA+0x4C ADC PDMA Current Transfer Data Register 0x0000_0000 Reserved Reserved Reserved CURDAT CURDAT Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:13] Reserved reset value.
  • Page 777 ISD94100 Series Technical Reference Manual ADC Control Register (EADC_CTL) Offset R/W Description Reset Value Register EADC_CTL EADC_BA+0x50 R/W ADC Control Register 0x0000_00C0 Reserved Reserved Reserved PDMAEN Reserved DMOF Reserved RESSEL ADCIEN3 ADCIEN2 ADCIEN1 ADCIEN0 ADCRST ADCEN Description Bits Reserved. Any values read should be ignored. When writing to this field always write with reset [31:12] Reserved value.
  • Page 778 ISD94100 Series Technical Reference Manual Description Bits Specific Sample Module ADC ADINT3 Interrupt Enable Bit The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion. If ADCIEN3 bit is set then conversion end interrupt ADCIEN3 request ADINT3 is generated.
  • Page 779 ISD94100 Series Technical Reference Manual ADC Sample Module Software Start Register (EADC_SWTRG) Offset R/W Description Reset Value Register EADC_SWTRG EADC_BA+0x54 ADC Sample Module Software Start Register 0x0000_0000 Reserved Reserved Reserved SWTRG SWTRG Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:13] Reserved reset value.
  • Page 780 ISD94100 Series Technical Reference Manual ADC Sample Module Start of Conversion Pending Flag Register (EADC_PENDSTS) Offset R/W Description Reset Value Register EADC_PENDSTS EADC_BA+0x58 R/W ADC Start of Conversion Pending Flag Register 0x0000_0000 Reserved Reserved Reserved STPF STPF Description Bits Reserved. Any values read should be ignored. When writing to this field always write with reset [31:13] Reserved value.
  • Page 781 ISD94100 Series Technical Reference Manual ADC Sample Module Overrun Flag Register (EADC_OVSTS) Offset R/W Description Reset Value Register ADC Sample Module Start of Conversion Overrun EADC_OVSTS EADC_BA+0x5C 0x0000_0000 Flag Register Reserved Reserved Reserved SPOVF SPOVF Bits Description Reserved. Any values read should be ignored. When writing to this field always write with Reserved [31:13] reset value.
  • Page 782 ISD94100 Series Technical Reference Manual ADC Sample Module 0~3 Control Registers (EADC_SCTL0~EADC_SCTL3) Offset R/W Description Reset Value Register EADC_SCTL0 EADC_BA+0x80 R/W ADC Sample Module 0 Control Register 0x0000_0000 EADC_SCTL1 EADC_BA+0x84 R/W ADC Sample Module 1 Control Register 0x0000_0000 EADC_SCTL2 EADC_BA+0x88 R/W ADC Sample Module 2 Control Register 0x0000_0000 EADC_SCTL3...
  • Page 783 ISD94100 Series Technical Reference Manual Description Bits ADC Sample Module Start of Conversion Trigger Source Selection 0H = Disable trigger. 1H = External trigger from EADC0_ST pin input. 2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. 3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. 4H = Timer0 overflow pulse trigger.
  • Page 784 ISD94100 Series Technical Reference Manual Description Bits ADC Sample Module Channel Selection 00H = EADC0_CH0. 01H = EADC0_CH1. 02H = EADC0_CH2. 03H = EADC0_CH3. 04H = EADC0_CH4. 05H = EADC0_CH5. [3:0] CHSEL 06H = EADC0_CH6. 07H = EADC0_CH7. 08H = EADC0_CH8. 09H = EADC0_CH9.
  • Page 785 ISD94100 Series Technical Reference Manual ADC Sample Module 4~12 Control Registers (EADC_SCTL4~EADC_SCTL12) Offset R/W Description Reset Value Register EADC_SCTL4 EADC_BA+0x90 R/W ADC Sample Module 4 Control Register 0x0000_0000 EADC_SCTL5 EADC_BA+0x94 R/W ADC Sample Module 5 Control Register 0x0000_0000 EADC_SCTL6 EADC_BA+0x98 R/W ADC Sample Module 6 Control Register 0x0000_0000 EADC_SCTL7...
  • Page 786 ISD94100 Series Technical Reference Manual Description Bits ADC Sample Module Start of Conversion Trigger Source Selection 0H = Disable trigger. 1H = External trigger from EADC0_ST pin input. 2H = ADC ADINT0 interrupt EOC pulse trigger. 3H = ADC ADINT1 interrupt EOC pulse trigger. 4H = Timer0 overflow pulse trigger.
  • Page 787 ISD94100 Series Technical Reference Manual Description Bits ADC Sample Module Channel Selection 00H = EADC0_CH0. 01H = EADC0_CH1. 02H = EADC0_CH2. 03H = EADC0_CH3. 04H = EADC0_CH4. 05H = EADC0_CH5. [3:0] CHSEL 06H = EADC0_CH6. 07H = EADC0_CH7. 08H = EADC0_CH8. 09H = EADC0_CH9.
  • Page 788 ISD94100 Series Technical Reference Manual ADC Interrupt Source Enable Control Registers (EADC_INTSRC0~EADC_INTSRC3) Offset R/W Description Reset Value Register EADC_INTSRC0 EADC_BA+0xD0 R/W ADC interrupt 0 Source Enable Control Register. 0x0000_0000 R/W ADC interrupt 1 Source Enable Control Register. EADC_INTSRC1 EADC_BA+0xD4 0x0000_0000 R/W ADC interrupt 2 Source Enable Control Register.
  • Page 789 ISD94100 Series Technical Reference Manual Description Bits Sample Module 6 Interrupt Enable Bit SPLIE6 0 = Sample Module 6 interrupt Disabled. 1 = Sample Module 6 interrupt Enabled. Sample Module 5 Interrupt Enable Bit SPLIE5 0 = Sample Module 5 interrupt Disabled. 1 = Sample Module 5 interrupt Enabled.
  • Page 790 ISD94100 Series Technical Reference Manual ADC Result Compare Register 0/1/2/3 (EADC_CMP0/1/2/3) Offset R/W Description Reset Value Register EADC_CMP0 EADC_BA+0xE0 R/W ADC Result Compare Register 0 0x0000_0000 EADC_CMP1 EADC_BA+0xE4 R/W ADC Result Compare Register 1 0x0000_0000 EADC_CMP2 EADC_BA+0xE8 R/W ADC Result Compare Register 2 0x0000_0000 EADC_CMP3 EADC_BA+0xEC...
  • Page 791 ISD94100 Series Technical Reference Manual Description Bits Compare Sample Module Selection 00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. 00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. 00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. 00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
  • Page 792 ISD94100 Series Technical Reference Manual ADC Status Register 0 (EADC_STATUS0) Offset R/W Description Reset Value Register EADC_STATUS0 EADC_BA+0xF0 ADC Status Register 0 0x0000_0000 Reserved Reserved VALID VALID Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:29] Reserved reset value.
  • Page 793 ISD94100 Series Technical Reference Manual ADC Status Register 2 (EADC_STATUS2) Offset R/W Description Reset Value Register EADC_STATUS2 EADC_BA+0xF8 R/W ADC Status Register 2 0x000F_0000 Reserved AVALID STOVF ADOVIF BUSY Reserved CHANNEL ADCMPO3 ADCMPO2 ADCMPO1 ADCMPO0 ADOVIF3 ADOVIF2 ADOVIF1 ADOVIF0 ADCMPF3 ADCMPF2 ADCMPF1 ADCMPF0...
  • Page 794 ISD94100 Series Technical Reference Manual Description Bits Busy/Idle(Read Only) [23] BUSY 0 = EADC is in idle state. 1 = EADC is busy at conversion. Reserved. Any values read should be ignored. When writing to this field always write with [22:21] Reserved reset value.
  • Page 795 ISD94100 Series Technical Reference Manual Description Bits ADC ADINT3 Interrupt Flag Overrun 0 = ADINT3 interrupt flag is not overwritten to 1. ADOVIF3 [11] 1 = ADINT3 interrupt flag is overwritten to 1. Note: This bit is cleared by writing 1 to it. ADC ADINT2 Interrupt Flag Overrun 0 = ADINT2 interrupt flag is not overwritten to 1.
  • Page 796 ISD94100 Series Technical Reference Manual Description Bits ADC ADINT3 Interrupt Flag 0 = No ADINT3 interrupt pulse received. 1 = ADINT3 interrupt pulse has been received. ADIF3 Note1: This bit is cleared by writing 1 to it. Note2:This bit indicates whether an ADC conversion of specific sample module has been completed ADC ADINT2 Interrupt Flag 0 = No ADINT2 interrupt pulse received.
  • Page 797 ISD94100 Series Technical Reference Manual ADC Status Register 3 (EADC_STATUS3) Offset R/W Description Reset Value Register EADC_STATUS3 EADC_BA+0xFC ADC Status Register 3 0x0000_001F Reserved Reserved Reserved Reserved CURSPL Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:5] Reserved reset value.
  • Page 798 ISD94100 Series Technical Reference Manual ADC Double Data Register n for Sample Module n (EADC_DDAT0~3) Offset R/W Description Reset Value Register EADC_DDAT0 EADC_BA+0x100 ADC Double Data Register 0 for Sample Module 0 0x0000_0000 EADC_DDAT1 EADC_BA+0x104 ADC Double Data Register 1 for Sample Module 1 0x0000_0000 EADC_DDAT2 EADC_BA+0x108...
  • Page 799 ISD94100 Series Technical Reference Manual ADC Power Management Register (EADC_PWRM) Offset R/W Description Reset Value Register EADC_PWRM EADC_BA+0x110 R/W ADC Power Management Register 0x0006_E012 Reserved Reserved LDOSUT LDOSUT Reserved PWDMOD PWUCALEN PWUPRDY Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:20] Reserved reset value.
  • Page 800 ISD94100 Series Technical Reference Manual ADC Channel Switch Presetting Control Register (EADC_CHSPC) Offset R/W Description Reset Value Register EADC_CHSPC EADC_BA+0x200 R/W ADC Channel Switch Presetting Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CHSPC Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:6] Reserved reset value.

  • Page 801: I 2 S Controller (I 2 S)

    ISD94100 Series Technical Reference Manual 6.17 S Controller (I 6.17.1 Overview The I S controller consists of I S protocol to interface with external audio CODEC. Two 16-level depth FIFO for reading path and writing path respectively and is capable of handling 8/16/24/32 bits audio data sizes.

  • Page 802: Block Diagram

    ISD94100 Series Technical Reference Manual 6.17.3 Block Diagram I2S_MCLK I2S Clock Generator I2S_LRCLK Transmit Contrl I2S_DO Tx Shift Register & TXFIFO Interface I2S_BCLK & Shift Clock dma_req Control Registers Receive dma_ack Control & Rx Shift Register I2S_DI RXFIFO Slave Figure 6.17-1 I S Controller Block Diagram 6.17.4 Basic Configuration ...

  • Page 803: Functional Description

    ISD94100 Series Technical Reference Manual 6.17.5 Functional Description 6.17.5.1 I S Clock The I S controller has four clock sources selected by I2SSEL (CLK_CLKSEL3[17:16]). The I clock rate must be slower than or equal to system clock rate. I2SSEL (CLK_CLKSEL3 [17:16]) I2SCKEN (CLK_APBCLK0 [29]) HIRC I2S_CLK...

  • Page 804: Figure 6.17-4 Slave Mode Interface Block Diagram

    ISD94100 Series Technical Reference Manual I2S_MCLK IS2_BCLK I2S_LRCLK Master Slave I2S_DO I2S_DI Figure 6.17-4 Slave mode Interface Block Diagram 6.17.5.3 I S Operation The I S controller supports MSB-justified, LSB-justified, and I S Philips standard data format. The I2S_LRCLK signal indicates which audio channel is in transferring. The bit count of an audio channel is defined by CHWIDTH (I2S_CTL0[29:28]), and the bit-width of data word in an audio channel is determined by DATWIDTH (I2S_CTL0[5:4]).

  • Page 805: Figure 6.17-7 I 2 S Data Format Timing Diagram (Format = 0X0 ; Chwidth≦Datwidth)

    ISD94100 Series Technical Reference Manual I2S_BCLK cycle of an audio channel. The MSB justified and LSB justified data format of I S protocol can be selected by FORMAT (I2S_CTL0[26:24]). I2S_BCLK I2S_LRCLK I2S_DI / LSB MSB I2S_DO Data width Data width Left channel Left channel of frame N Right channel of frame N...

  • Page 806: Figure 6.17-10 Standard Pcm Audio Timing Diagram (Format = 0X4 ; Chwidth≦Datwidth)

    ISD94100 Series Technical Reference Manual PCM with MSB justified, and PCM with LSB justified data format. I2S_BCLK I2S_LRCLK I2S_DI / LSB MSB I2S_DO Data width Data width Left channel Left channel of frame N Right channel of frame N of frame N+1 Figure 6.17-10 Standard PCM Audio Timing Diagram (FORMAT = 0x4 ;...

  • Page 807: Figure 6.17-13 Tdm 6-Channel Audio Format With 24-Bit Data In 32-Bit Channel Block (Pcm Standard Data Format; Format=0X4)

    ISD94100 Series Technical Reference Manual (I2S_CTL0[29:28]) respectively. Note that the TDM PCM mode supports 16-bit, 24-bit, 32-bit audio data word (excluding 8-bit data), and the hardware will set the bit-width of transmitting data as 16-bit if DATWIDTH (I2S_CTL0[5:4]) is 0x0. The pulse width of frame start signal is also selected by PCMSYNC (I2S_CTL0[27]).
  • Page 808 ISD94100 Series Technical Reference Manual 6.17.5.5 Zero Crossing When playing the audio by I S controller, the output transmitting data comes from the memory by PDMA or by CPU. However, there may be some pop noise which induces the uncomfortable hearing if the playing sound volume is changed greatly by user.

  • Page 809: Figure 6.17-16 I 2 S Interrupts

    ISD94100 Series Technical Reference Manual CH0ZCIEN CH0ZCIF CH1ZCIEN CH1ZCIF TXTHIEN CH2ZCIEN I2STXINT CH2ZCIF TXTHIF CH3ZCIEN TXOVFIEN TXOVIF CH3ZCIF TXUDFIEN CH4ZCIEN I2SINT CH4ZCIF TXUDIF RXTHIEN CH5ZCIEN CH5ZCIF RXTHIF RXOVFIEN CH6ZCIEN I2SRXINT CH6ZCIF RXOVIF CH7ZCIEN RXUDFIEN RXUDIF CH7ZCIF Figure 6.17-16 I S Interrupts 6.17.5.8 FIFO Operation In 2-channel I S or PCM protocol, the bit-width of audio data in a channel block can be 8, 16, 24,...

  • Page 810: Figure 6.17-17 Fifo Contents For Various 2-Channel Audio Modes

    ISD94100 Series Technical Reference Manual Mono 8-bit data mode Stereo 8-bit data mode, ORDER (I2S_CTL0[7]) = 0 LEFT+1 RIGHT+1 LEFT RIGHT Stereo 8-bit data mode, ORDER (I2S_CTL0[7]) = 1 RIGHT+1 LEFT+1 RIGHT LEFT Mono 16-bit data mode Stereo 16-bit data mode, ORDER (I2S_CTL0[7]) = 0 LEFT RIGHT Stereo 16-bit data mode, ORDER (I2S_CTL0[7]) = 1...

  • Page 811: Figure 6.17-18 Fifo Contents For Various 4-Channel Audio Modes

    ISD94100 Series Technical Reference Manual Mono 16-bit data mode Stereo 16-bit data mode, ORDER (I2S_CTL0[7]) = 0 Stereo 16-bit data mode, ORDER (I2S_CTL0[7]) = 1 Mono 24-bit data mode, ORDER (I2S_CTL0[7]) = 0 Redundant bits Mono 24-bit data mode, ORDER (I2S_CTL0[7]) = 1 Redundant bits Stereo 24-bit data mode, ORDER (I2S_CTL0[7]) = 0 Redundant bits...

  • Page 812: Figure 6.17-19 Fifo Contents For Various 6-Channel Audio Modes (Part-1)

    ISD94100 Series Technical Reference Manual In 6-channel TDM PCM data format, the bit-width of audio data in a channel block can be 16, 24, or 32 bits. The memory arrangements of audio data for various settings are shown Figure 6.17-19. In 16-bit audio data transmission, ORDER (I2S_CTL0[7]) can be used to swap the audio data of even and odd channels which are stored in transmitting and receiving FIFO.

  • Page 813: Figure 6.17-20 Fifo Contents For Various 6-Channel Audio Modes (Part-2)

    ISD94100 Series Technical Reference Manual Stereo 24-bit data mode, ORDER (I2S_CTL0[7]) = 0 Redundant bits Redundant bits Redundant bits Redundant bits Redundant bits Redundant bits Stereo 24-bit data mode, ORDER (I2S_CTL0[7]) = 1 Redundant bits Redundant bits Redundant bits Redundant bits Redundant bits Redundant bits Mono 32-bit data mode...

  • Page 814: Register Map

    ISD94100 Series Technical Reference Manual 6.17.6 Register Map R: Read only, W: Write only, R/W: Both read and write Register Offset R/W Description Reset Value I2S Base Address I2S_BA = 0x4004_8000 I2S_CTL0 I2S_BA+0x00 R/W I S Control Register 0 0x0000_0000 I2S_CTL1 I2S_BA+0x20 R/W I...

  • Page 815: Register Description

    ISD94100 Series Technical Reference Manual 6.17.7 Register Description I2S Control Register 0 (I2S_CTL0) Register Offset R/W Description Reset Value I2S_CTL0 I2S_BA+0x00 R/W I S Control Register 0 0x0000_0000 TDMCHNUM CHWIDTH PCMSYNC FORMAT RXLCH Reserved RXPDMAEN TXPDMAEN RXFBCLR TXFBCLR FLZCDEN FRZCDEN MCLKEN Reserved SLAVE...
  • Page 816 ISD94100 Series Technical Reference Manual Data Format Selection 000 = I S standard data format. 001 = I S with MSB justified. 010 = I S with LSB justified. [26:24] FORMAT 011 = Reserved. Do not use. 100 = PCM standard data format. 101 = PCM with MSB justified.
  • Page 817 ISD94100 Series Technical Reference Manual Master Clock Enable Control If MCLKEN is set to 1, I S controller will generate master clock on I2S_MCLK pin for external audio devices. [15] MCLKEN 0 = Master clock Disabled. 1 = Master clock Enabled. Reserved.
  • Page 818 ISD94100 Series Technical Reference Manual I2S Control Register 1 (I2S_CTL1) Register Offset R/W Description Reset Value I2S_CTL1 I2S_BA+0x20 R/W I S Control Register 1 0x0000_0000 Reserved PB16ORD PBWIDTH Reserved RXTH Reserved TXTH CH7ZCEN CH6ZCEN CH5ZCEN CH4ZCEN CH3ZCEN CH2ZCEN CH1ZCEN CH0ZCEN Bits Description Reserved.
  • Page 819 ISD94100 Series Technical Reference Manual Receive FIFO Threshold Level 0000 = 1 data word in receive FIFO. 0001 = 2 data words in receive FIFO. 0010 = 3 data words in receive FIFO. [19:16] RXTH …. 1110 = 15 data words in receive FIFO. 1111 = 16 data words in receive FIFO.
  • Page 820 ISD94100 Series Technical Reference Manual Channel4 Zero-cross Detect Enable Control 0 = channel4 zero-cross detect Disabled. 1 = channel4 zero-cross detect Enabled. Note1: This bit is available while multi-channel PCM mode and TDMCHNUM CH4ZCEN (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.
  • Page 821 ISD94100 Series Technical Reference Manual I2S Clock Divider (I2S_CLKDIV) Register Offset R/W Description Reset Value I2S_CLKDIV I2S_BA+0x04 R/W I S Clock Divider Register 0x0000_0000 Reserved Reserved BCLKDIV BCLKDIV Reserved MCLKDIV Bits Description Reserved. Any values read should be ignored. When writing to this field always write with [31:18] Reserved reset value.
  • Page 822 ISD94100 Series Technical Reference Manual I2S Interrupt Enable Register (I2S_IEN) Register Offset R/W Description Reset Value I2S_IEN I2S_BA+0x08 R/W I S Interrupt Enable Register 0x0000_0000 Reserved CH7ZCIEN CH6ZCIEN CH5ZCIEN CH4ZCIEN CH3ZCIEN CH2ZCIEN CH1ZCIEN CH0ZCIEN Reserved TXTHIEN TXOVFIEN TXUDFIEN Reserved RXTHIEN RXOVFIEN RXUDFIEN Bits...
  • Page 823 ISD94100 Series Technical Reference Manual Channel3 Zero-cross Interrupt Enable Control 0 = Interrupt Disabled. 1 = Interrupt Enabled. [19] CH3ZCIEN Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
  • Page 824 ISD94100 Series Technical Reference Manual Receive FIFO Overflow Interrupt Enable Control 0 = Interrupt Disabled. RXOVFIEN 1 = Interrupt Enabled. Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1 Receive FIFO Underflow Interrupt Enable Control 0 = Interrupt Disabled.
  • Page 825 ISD94100 Series Technical Reference Manual I2S Status Register 0 (I2S_STATUS0) Register Offset R/W Description Reset Value I2S_STATUS0 I2S_BA+0x0C R/W I S Status Register 0 0x0014_1000 Reserved Reserved TXBUSY TXEMPTY TXFULL TXTHIF TXOVIF TXUDIF Reserved RXEMPTY RXFULL RXTHIF RXOVIF RXUDIF Reserved DATACH I2STXINT I2SRXINT...
  • Page 826 ISD94100 Series Technical Reference Manual Transmit FIFO Underflow Interrupt Flag 0 = No underflow. 1 = Underflow. [16] TXUDIF Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. Note2: Write 1 to clear this bit to 0.
  • Page 827 ISD94100 Series Technical Reference Manual S Transmit Interrupt (Read Only) I2STXINT 0 = No transmit interrupt. 1 = Transmit interrupt. S Receive Interrupt (Read Only) I2SRXINT 0 = No receive interrupt. 1 = Receive interrupt. S Interrupt Flag (Read Only) 0 = No I S interrupt.
  • Page 828 ISD94100 Series Technical Reference Manual I2S Status Register 1 (I2S_STATUS1) Register Offset R/W Description Reset Value I2S_STATUS1 I2S_BA+0x24 R/W I S Status Register 1 0x0000_0000 Reserved Reserved RXCNT Reserved TXCNT CH7ZCIF CH6ZCIF CH5ZCIF CH4ZCIF CH3ZCIF CH2ZCIF CH1ZCIF CH0ZCIF Bits Description Reserved.
  • Page 829 ISD94100 Series Technical Reference Manual Channel7 Zero-cross Interrupt Flag It indicates channel7 next sample data sign bit is changed or all data bits are zero. 0 = No zero-cross in channel7. CH7ZCIF 1 = Channel7 zero-cross is detected. Note1: Write 1 to clear this bit to 0. Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
  • Page 830 ISD94100 Series Technical Reference Manual Channel1 Zero-cross Interrupt Flag It indicates channel1 next sample data sign bit is changed or all data bits are zero. 0 = No zero-cross in channel1. CH1ZCIF 1 = Channel1 zero-cross is detected. Note1: Write 1 to clear this bit to 0. Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
  • Page 831 ISD94100 Series Technical Reference Manual I2S Transmit FIFO (I2S_TXFIFO) Register Offset R/W Description Reset Value I2S_TXFIFO I2S_BA+0x10 S Transmit FIFO Register 0x0000_0000 TXFIFO TXFIFO TXFIFO TXFIFO Bits Description Transmit FIFO Bits S contains 16 words (16x32 bit) data buffer for data transmit. Write data to this register to [31:0] TXFIFO prepare data for transmit.
  • Page 832 ISD94100 Series Technical Reference Manual I2S Receive FIFO (I2S_RXFIFO) Register Offset R/W Description Reset Value I2S_RXFIFO I2S_BA+0x14 S Receive FIFO Register 0x0000_0000 RXFIFO RXFIFO RXFIFO RXFIFO Bits Description Receive FIFO Bits [31:0] RXFIFO S contains 16 words (16x32 bit) data buffer for data receive. Read this register to get data in FIFO.

  • Page 833: Usb 1.1 Device Controller (Usbd)

    ISD94100 Series Technical Reference Manual 6.18 USB 1.1 Device Controller (USBD) 6.18.1 Overview There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/isochronous transfer types.

  • Page 834: Block Diagram

    ISD94100 Series Technical Reference Manual 6.18.3 Block Diagram Clock NVIC Generator VBUS Detection VBUS Interrupt Detection DPLL control control De-bouncing status registers USB_D+ APB Bus RXDP Endpoint USB_D- RXDM Control SRAM USB_VBUS Buffer Control Bytes) Transceiver Figure 6.18-1 USB Block Diagram 6.18.4 Basic Configuration The role of USB frame is determined by USBROLE (SYS_USBPHY[1:0]).

  • Page 835: Functional Description

    ISD94100 Series Technical Reference Manual 6.18.5 Functional Description 6.18.5.1 Serial Interface Engine (SIE) The SIE is the front-end of the device controller and handles most of the USB packet protocol. The SIE typically comprehends signaling up to the transaction level. The functions that it handles could include: ...

  • Page 836: Figure 6.18-2 Nevwk Interrupt Operation Flow

    ISD94100 Series Technical Reference Manual Wake Up Enable System Power Down System Wake-up Wait 20ms NEVWK Interrupt Figure 6.18-2 NEVWK Interrupt Operation Flow The USB interrupt is used to notify users of any USB event on the bus, and user can read EPSTS (USBD_EPSTS0 and USBD_EPSTS1) and EPEVT11~0 (USBD_INTSTS[27:16]) to take necessary responses.

  • Page 837: Figure 6.18-3 Endpoint Sram Structure

    ISD94100 Series Technical Reference Manual USBD_SRAM = USBD_BA + 0x0100h USB SRAM Start Address Setup Token Buffer: 8 bytes BUFSEG0 = 0x008 EP0 SA = USBD_BA + 0x0108h EP0 SRAM Buffer: 64 bytes MXPLD0 = 0x40 BUFSEG1 = 0x048 EP1 SA = USBD_BA + 0x0148h EP1 SRAM Buffer: 64 bytes MXPLD1 = 0x40 BUFSEG2 = 0x088...

  • Page 838: Figure 6.18-5 Data Out Transfer

    ISD94100 Series Technical Reference Manual Alternatively, when USB host wants to transmit data to the OUT endpoint in the device controller, hardware will buffer these data to the specified endpoint buffer. After this transaction is completed, hardware will record the data length in specified USBD_MXPLDx register and de-assert the internal signal “Out_Rdy”.

  • Page 839: Register Map

    ISD94100 Series Technical Reference Manual 6.18.6 Register Map R: read only, W: write only, R/W: both read and write Offset R/W Description Reset Value Register USBD Base Address: USBD_BA = 0x400C_0000 USBD_INTEN USBD_BA+0x000 R/W USB Device Interrupt Enable Register 0x0000_0000 USBD_INTSTS USBD_BA+0x004 R/W USB Device Interrupt Event Status Register...
  • Page 840 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register USBD Base Address: USBD_BA = 0x400C_0000 USBD_CFG3 USBD_BA+0x538 R/W Endpoint 3 Configuration Register 0x0000_0000 Endpoint 3 Set Stall and Clear In/Out Ready Control USBD_CFGP3 USBD_BA+0x53C 0x0000_0000 Register USBD_BUFSEG4 USBD_BA+0x540 R/W Endpoint 4 Buffer Segmentation Register 0x0000_0000 USBD_MXPLD4...
  • Page 841 ISD94100 Series Technical Reference Manual Offset R/W Description Reset Value Register USBD Base Address: USBD_BA = 0x400C_0000 Register USBD_BUFSEG10 USBD_BA+0x5A0 R/W Endpoint 10 Buffer Segmentation Register 0x0000_0000 USBD_MXPLD10 USBD_BA+0x5A4 R/W Endpoint 10 Maximal Payload Register 0x0000_0000 USBD_CFG10 USBD_BA+0x5A8 R/W Endpoint 10 Configuration Register 0x0000_0000 Endpoint 10 Set Stall and Clear In/Out Ready Control USBD_CFGP10...

  • Page 842: Register Description

    ISD94100 Series Technical Reference Manual 6.18.7 Register Description USB Interrupt Enable Register (USBD_INTEN) Offset R/W Description Reset Value Register USBD_INTEN USBD_BA+0x000 R/W USB Device Interrupt Enable Register 0x0000_0000 Reserved Reserved INNAKEN Reserved WKEN Reserved SOFIEN NEVWKIEN VBDETIEN USBIEN BUSIEN Description Bits Reserved.
  • Page 843 ISD94100 Series Technical Reference Manual USB Event Interrupt Enable Bit USBIEN 0 = USB event interrupt Disabled. 1 = USB event interrupt Enabled. Bus Event Interrupt Enable Bit BUSIEN 0 = BUS event interrupt Disabled. 1 = BUS event interrupt Enabled. Sep 9, 2019 Page 843 of 928 Rev1.09...
  • Page 844 ISD94100 Series Technical Reference Manual USB Interrupt Event Status Register (USBD_INTSTS) Offset R/W Description Reset Value Register USBD_INTSTS USBD_BA+0x004 R/W USB Device Interrupt Event Status Register 0x0000_0000 SETUP Reserved EPEVT11 EPEVT10 EPEVT9 EPEVT8 EPEVT7 EPEVT6 EPEVT5 EPEVT4 EPEVT3 EPEVT2 EPEVT1 EPEVT0 Reserved Reserved...
  • Page 845 ISD94100 Series Technical Reference Manual Endpoint 6’s USB Event Status 0 = No event occurred in endpoint 6. [22] EPEVT6 1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[22] or USBD_INTSTS[1].
  • Page 846 ISD94100 Series Technical Reference Manual 1 = USB event occurred, check EPSTS (USBD_EPSTS0 and USBD_EPSTS1) to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[1] or EPEVT11~0 (USBD_INTSTS[27:16] and SETUP (USBD_INTSTS[31]). BUS Interrupt Status The BUS event means that there is one of the suspend or the resume function in the bus. BUSIF 0 = No BUS event occurred.
  • Page 847 ISD94100 Series Technical Reference Manual USB Device Function Address Register (USBD_FADDR) A 7-bit value is used as the address of a device on the USB BUS. Offset R/W Description Reset Value Register USBD_FADDR USBD_BA+0x008 R/W USB Device Function Address Register 0x0000_0000 Reserved Reserved...
  • Page 848 ISD94100 Series Technical Reference Manual USB Endpoint Status Register (USBD_EPSTS) Offset R/W Description Reset Value Register USBD_EPSTS USBD_BA+0x00C USB Device Endpoint Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:8] Reserved reset value.
  • Page 849 ISD94100 Series Technical Reference Manual USB Bus Status and Attribution Register (USBD_ATTR) Offset R/W Description Reset Value Register USBD_ATTR USBD_BA+0x010 R/W USB Device Bus Status and Attribution Register 0x0000_0040 Reserved Reserved Reserved BYTEM Reserved DPPUEN USBEN Reserved RWAKEUP PHYEN TOUT RESUME SUSPEND USBRST...
  • Page 850 ISD94100 Series Technical Reference Manual Resume Status 0 = No bus resume. RESUME 1 = Resume from suspend. Note: This bit is read only. Suspend Status 0 = Bus no suspend. SUSPEND 1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping. Note: This bit is read only.
  • Page 851 ISD94100 Series Technical Reference Manual USB Device VBUS Detection Register (USBD_VBUSDET) Offset R/W Description Reset Value Register USBD_VBUSDET USBD_BA+0x014 USB Device VBUS Detection Register 0x0000_0000 Reserved Reserved Reserved Reserved VBUSDET Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:1] Reserved reset value.
  • Page 852 ISD94100 Series Technical Reference Manual USB SETUP Token Buffer Segmentation Register (USBD_STBUFSEG) Offset R/W Description Reset Value Register USBD_STBUFSEG USBD_BA+0x018 R/W SETUP Token Buffer Segmentation Register 0x0000_0000 Reserved Reserved Reserved STBUFSEG STBUFSEG Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 853 ISD94100 Series Technical Reference Manual USB Endpoint Status Register 0 (USBD_EPSTS0) Offset R/W Description Reset Value Register USBD_EPSTS0 USBD_BA+0x020 USB Device Endpoint Status Register 0 0x0000_0000 EPSTS7 EPSTS6 EPSTS5 EPSTS4 EPSTS3 EPSTS2 EPSTS1 EPSTS0 Description Bits Endpoint 7 Status These bits are used to indicate the current status of this endpoint 0000 = In ACK.
  • Page 854 ISD94100 Series Technical Reference Manual 0000 = In ACK. 0001 = In NAK. 0010 = Out Packet Data0 ACK. 0011 = Setup ACK. 0110 = Out Packet Data1 ACK. 0111 = Isochronous transfer end. Endpoint 3 Status These bits are used to indicate the current status of this endpoint 0000 = In ACK.
  • Page 855 ISD94100 Series Technical Reference Manual USB Endpoint Status Register 1 (USBD_EPSTS1) Offset R/W Description Reset Value Register USBD_EPSTS1 USBD_BA+0x024 USB Device Endpoint Status Register 1 0x0000_0000 Reserved Reserved EPSTS11 EPSTS10 EPSTS9 EPSTS8 Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:16] Reserved reset value.
  • Page 856 ISD94100 Series Technical Reference Manual Endpoint 8 Status These bits are used to indicate the current status of this endpoint 0000 = In ACK. 0001 = In NAK. [3:0] EPSTS8 0010 = Out Packet Data0 ACK. 0011 = Setup ACK. 0110 = Out Packet Data1 ACK.
  • Page 857 ISD94100 Series Technical Reference Manual USB Frame Number Register (USBD_FN) Offset R/W Description Reset Value Register USBD_FN USBD_BA+0x08C USB Frame number Register 0x0000_0XXX Reserved Reserved Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:11] Reserved reset value.
  • Page 858 ISD94100 Series Technical Reference Manual USB Drive SE0 Register (USBD_SE0) Offset R/W Description Reset Value Register USBD_SE0 USBD_BA+0x090 R/W USB Device Drive SE0 Control Register 0x0000_0001 Reserved Reserved Reserved Reserved Description Bits Reserved. Any values read should be ignored. When writing to this field always write with [31:1] Reserved reset value.
  • Page 859 ISD94100 Series Technical Reference Manual USB Buffer Segmentation Register (USBD_BUFSEGx) Offset R/W Description Reset Value Register USBD_BUFSEG0 USBD_BA+0x500 R/W Endpoint 0 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG1 USBD_BA+0x510 R/W Endpoint 1 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG2 USBD_BA+0x520 R/W Endpoint 2 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG3 USBD_BA+0x530...
  • Page 860 ISD94100 Series Technical Reference Manual USB Maximal Payload Register (USBD_MXPLDx) Offset R/W Description Reset Value Register USBD_MXPLD0 USBD_BA+0x504 R/W Endpoint 0 Maximal Payload Register 0x0000_0000 USBD_MXPLD1 USBD_BA+0x514 R/W Endpoint 1 Maximal Payload Register 0x0000_0000 USBD_MXPLD2 USBD_BA+0x524 R/W Endpoint 2 Maximal Payload Register 0x0000_0000 USBD_MXPLD3 USBD_BA+0x534...
  • Page 861 ISD94100 Series Technical Reference Manual When the register is read by CPU, For IN token, the value of MXPLD is indicated by the data length be transmitted to host For OUT token, the value of MXPLD is indicated the actual data length receiving from host. Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
  • Page 862 ISD94100 Series Technical Reference Manual USB Configuration Register (USBD_CFGx) Offset R/W Description Reset Value Register USBD_CFG0 USBD_BA+0x508 R/W Endpoint 0 Configuration Register 0x0000_0000 USBD_CFG1 USBD_BA+0x518 R/W Endpoint 1 Configuration Register 0x0000_0000 USBD_CFG2 USBD_BA+0x528 R/W Endpoint 2 Configuration Register 0x0000_0000 USBD_CFG3 USBD_BA+0x538 R/W Endpoint 3 Configuration Register 0x0000_0000...
  • Page 863 ISD94100 Series Technical Reference Manual 1 = DATA1 PID. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit. Endpoint STATE 00 = Endpoint is Disabled. [6:5] STATE 01 = Out endpoint.
  • Page 864 ISD94100 Series Technical Reference Manual USB Extra Configuration Register (USBD_CFGPx) Offset R/W Description Reset Value Register Endpoint 0 Set Stall and Clear In/Out Ready Control USBD_CFGP0 USBD_BA+0x50C 0x0000_0000 Register Endpoint 1 Set Stall and Clear In/Out Ready Control USBD_CFGP1 USBD_BA+0x51C 0x0000_0000 Register Endpoint 2 Set Stall and Clear In/Out Ready Control...
  • Page 865 ISD94100 Series Technical Reference Manual 1 = Set the device to respond STALL automatically. Clear Ready When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.

  • Page 866: Digital Microphone Inputs (Dmic)

    ISD94100 Series Technical Reference Manual 6.19 Digital Microphone Inputs (DMIC) 6.19.1 Overview Using the dual channel digital PDM (Pulse Density Modulation) microphone interface (DMIC_CLK0, DMIC_DAT0, DMIC_CLK1 and DMIC_DAT1 pins) that are handled four digital PDM microphone inputs. Both DMIC_DAT0 and DMIC_DAT1 inputs are able to handle two digital microphones by selecting them alternately for each half of the clock cycle.

  • Page 867: Functional Description

    ISD94100 Series Technical Reference Manual – The DMIC module is reset by DMICRST (SYS_IPRST1[15]).  Pin configuration Pin Name GPIO Group PA.0 MFP3 DMIC_DAT0 PB.5 MFP5 PD.6 MFP4 PA.1 MFP3 DMIC_CLK0 PB.6 MFP5 PD.5 MFP4 DMIC PA.2 MFP3 DMIC_DAT1 PB.3 MFP3 PD.4 MFP4...

  • Page 868: Table 6.19.5-1 Example For Dmic Bus Clock And Osr Configuring

    ISD94100 Series Technical Reference Manual DMIC_MCLK. 6.19.5.3 Determine DMIC Bus Clock and DMIC Working Main Clock Determine DMIC working main clock (DMIC_MCLK) by: F_DMIC_MCLK = Fs * K; K must be 500 or 256. Where Fs is sample rate, and F_DMIC_MCLK is the frequency of DMIC_MCLK. Determine DMIC bus clock (DMIC_CLK) by: F_DMIC_CLK = Fs * OSR.

  • Page 869: Figure 6.19-3 Typical Connection To Two Digital Microphones Sharing A Common Data Line

    ISD94100 Series Technical Reference Manual DMIC_CLKn Digital MIC DMIC_DATn Digital MIC Note: n = 0 or 1 Figure 6.19-3 Typical connection to two digital microphones sharing a common data line Latched PDM Data on Falling Clock Edge Latched PDM Data on Rising Clock Edge DMIC Bus Clock on DMIC_CLK0 pin High Z MIC0...

  • Page 870: Figure 6.19-5 Dmic Fifo Contents For Various Settings

    ISD94100 Series Technical Reference Manual DMIC_CTL[9:8] = 00, DMIC_CTL[3:0] = 0001 Data on Falling Clock Edge of DMIC_DAT0 pin Redundant bits DMIC_CTL[9:8] = 10, DMIC_CTL[3:0] = 1000 Data on Falling Clock Edge of DMIC_DAT1 pin Redundant bits DMIC_CTL[9:8] = 00, DMIC_CTL[3:0] = 0011 Data on Falling Clock Edge of DMIC_DAT0 pin Redundant bits Data on Rising Clock Edge of DMIC_DAT0 pin...

  • Page 871: Register Map

    ISD94100 Series Technical Reference Manual 6.19.6 Register Map R: read only, W: write only, R/W: both read and write. Offset R/W Description Reset Value Register DMIC Base Address: DMIC_BA = 0x4006_3000 DMIC_CTL DMIC_BA+0x00 R/W DMIC Control Register 0xB7CD_0000 DMIC_DIV DMIC_BA+0x04 R/W DMIC Clock Divider Register 0x0000_0307 DMIC_STATUS...

  • Page 872: Register Description

    ISD94100 Series Technical Reference Manual 6.19.7 Register Description DMIC Control Register (DMIC_CTL) Offset R/W Description Reset Value Register DMIC_CTL DMIC_BA+0x00 R/W DMIC Control Register 0xB7CD_0000 Reserved Reserved Reserved LCHEDGE23 LCHEDGE01 Reserved CHEN3 CHEN2 CHEN1 CHEN0 Bits Description Reserved. Any values read should be ignored. When writing to this field always write [31:10] Reserved with reset value.
  • Page 873 ISD94100 Series Technical Reference Manual Channel 3 Enable Bit Set this bit to 1 to enable DMIC channel 3 operation. CHEN3 0 = Channel 3 Disabled. 1 = Channel 3 Enabled. Channel 2 Enable Bit Set this bit to 1 to enable DMIC channel 2 operation. CHEN2 0 = Channel 2 Disabled.
  • Page 874 ISD94100 Series Technical Reference Manual DMIC Clock Divider Register (DMIC_DIV) Offset R/W Description Reset Value Register DMIC_DIV DMIC_BA+0x04 R/W DMIC Clock Divider Register 0x0000_0307 Reserved FCLR THIE MCLKDIV PCLKDIV Bits Description Reserved. Any values read should be ignored. When writing to this field always write Reserved [31:24] with reset value.
  • Page 875 ISD94100 Series Technical Reference Manual Sep 9, 2019 Page 875 of 928 Rev1.09...
  • Page 876 ISD94100 Series Technical Reference Manual DMIC Status Register (DMIC_STATUS) Offset R/W Description Reset Value Register DMIC_STATUS DMIC_BA+0x08 DMIC Status Register 0x0000_0002 Reserved Reserved Reserved FIFOPTR FIFOPTR Reserved THIF EMPTY FULL Bits Description Reserved. Any values read should be ignored. When writing to this field always write Reserved [31:9] with reset value.
  • Page 877 ISD94100 Series Technical Reference Manual DMIC PDMA Control Register(DMIC_PDMACTL) Offset R/W Description Reset Value Register DMIC_PDMACTL DMIC_BA+0x0C R/W DMIC PDMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDMAEN Bits Description Reserved. Any values read should be ignored. When writing to this field always write Reserved [31:1] with reset value.
  • Page 878 ISD94100 Series Technical Reference Manual DMIC FIFO Data Output Register (DMIC_FIFO) Offset R/W Description Reset Value Register DMIC_FIFO DMIC_BA+0x10 DMIC FIFO Data Output Register 0x0000_0000 Reserved FIFO FIFO FIFO Bits Description Reserved. Any values read should be ignored. When writing to this field always write Reserved [31:24] with reset value.

  • Page 879: Voice Active Detection (Vad)

    ISD94100 Series Technical Reference Manual 6.20 Voice Active Detection (VAD) 6.20.1 Overview The Voice Active Detection (VAD) analyses the PCM data from DMIC channel 0, and it consists of a SINC filter, a biquad filter and a VAD module. The idea of the VAD is to calculate the short term signal power and long term signal power of the input signal, and then compare the short term power with the short term power threshold.

  • Page 880: Figure 6.20-2 Vad Clock Control Diagram

    ISD94100 Series Technical Reference Manual HIRC DMIC Path PCLK1 (DMIC_CLK) DMIC_MCLK 1/(1+PCLKDIV) PLLFOUT 1/(1+MCLKDIV) DMIC_CLK DMICCKEN (CLK_APBCLK0[15]) VAD Path (VAD_CLK) ACTIVE (VAD_STATUS0[31]) ACTCL (VAD_SINCCTL[30]) VADEN (VAD_SINCCTL[31]) CHEN0 (DMIC_CTL[0]) Note: PCLKDIV = DMIC_DIV[7:0] MCLKDIV = DMIC_DIV[15:8] ACTCL (VAD_SINCCTL[30]) (VAD_SINCCTL[29]) Figure 6.20-2 VAD Clock Control Diagram 6.20.5.2 VAD Data Control The VAD data diagram is shown in Figure 6.20-3.

  • Page 881: Figure 6.20-3 Vad Data Diagram

    ISD94100 Series Technical Reference Manual Figure 6.20-3 VAD Data Diagram 6.20.5.3 SINC Filter For the SINC filter, it has three over sampling rate (OSR) configuration that controlled by register SINCOSR (VAD_SINC_CTL[11:8]): OSR48, OSR64, OSR96. For the three OSR options, the DMIC bus clock (DMIC_CLK) will be (Fs x 48) kHz, (Fs x 64) kHz or (Fs x 96) kHz, where Fs is sample rate.

  • Page 882: Figure 6.20-4 Vad Decision Tree

    ISD94100 Series Technical Reference Manual ACTIVE=0 Short Term Power Long Term Power STAT Formula Formula LTAT To get STP To get LTP LTP> LTTHRE STP >STTHREHWM (LTTHRE) =|LTP-STP| =|LTP(LTTHRE)-STP| Note: STAT = VAD_CTL0[7:0] DEV >DEVTHRE LTAT = VAD_CTL0[19:16] STP = VAD_STATUS0[15:0] LTP = VAD_STATUS1[31:16] STTHREHWM = VAD_CTL1[15:0] LTTHRE = VAD_CTL2[31:16]...

  • Page 883: Table 6.20.5-1 Short Term Power Attack Time Selection

    ISD94100 Series Technical Reference Manual 0xCC or 0xBB may be used. STAT 0x99 0xAA 0xBB 0xCC (VAD_CTL0[7:0]) Attack Time 16 ms 8 ms 4 ms 2 ms Table 6.20.5-1 Short Term Power Attack Time Selection Long term power attack time: LTAT (VAD_CTL0[19:16]) = 0x5. If slower attack is desired, e.g., if the target environment is relatively stable, 0x4 may be used.

  • Page 884: Table 6.20.5-3 Power Threshold Reference

    ISD94100 Series Technical Reference Manual Step 5: Set Deviation Threshold with a value right below Deviation values obtained from step Set deviation threshold DEVTHRE (VAD_CTL3[15:0]) lower than deviation power DEV (VAD_STATUS1[15:0]) read out values. Short term power threshold STTHREHWM (VAD_CTL1) and deviation threshold DEVTHRE (VAD_CTL3[15:0]) can be fine-tuned to achieve the sensitivity to desired human speaking volume.

  • Page 885: Register Map

    ISD94100 Series Technical Reference Manual 6.20.6 Register Map R: read only, W: write only, R/W: both read and write. Register Offset R/W Description Reset Value VAD Base Address: VAD_BA = 0x4006_3100 VAD_SINCCTL VAD_BA+0x00 R/W VAD SINC Filter Control Register 0x0000_0008 VAD_BIQCTL0 VAD_BA+0x04 R/W VAD Biquad Filter Control Register 0...

  • Page 886: Register Description

    ISD94100 Series Technical Reference Manual 6.20.7 Register Description VAD SINC Filter Control Register (VAD_SINCCTL) Register Offset R/W Description Reset Value VAD_SINCCTL VAD_BA+0x00 R/W VAD SINC Filter Control Register 0x0000_0008 VADEN ACTCL DATAOFF Reserved Reserved Reserved SINCOSR Reserved Bits Description VAD Enable Control 0 = VAD Disabled.
  • Page 887 ISD94100 Series Technical Reference Manual 010 = Down sample 96 Others = Reserved. Do not use. Reserved. Any values read should be ignored. When writing to this field always write [7:0] Reserved with reset value. Sep 9, 2019 Page 887 of 928 Rev1.09...
  • Page 888 ISD94100 Series Technical Reference Manual VAD Biquad Filter Control Register 0 (VAD_BIQCTL0) Register Offset R/W Description Reset Value VAD_BIQCTL0 VAD_BA+0x04 R/W VAD Biquad Filter Control Register 0 0x0000_0000 BIQA2 BIQA2 BIQA1 BIQA1 Bits Description VAD Biquad Filter Coefficient [31:16] BIQA2 Biquad Filter Coefficient a2, in 3 intergers + 13 fractional bits.
  • Page 889 ISD94100 Series Technical Reference Manual VAD Biquad Filter Control Register 1 (VAD_BIQCTL1) Register Offset R/W Description Reset Value VAD_BIQCTL1 VAD_BA+0x08 R/W VAD Biquad Filter Control Register 1 0x0000_0000 BIQB1 BIQB1 BIQB0 BIQB0 Bits Description VAD Biquad Filter Coefficient [31:16] BIQB1 Biquad Filter Coefficient b1, in 3 intergers + 13 fractional bits.
  • Page 890 ISD94100 Series Technical Reference Manual VAD Biquad Filter Control Register 2 (VAD_BIQCTL2) Register Offset R/W Description Reset Value VAD_BIQCTL2 VAD_BA+0x0C R/W VAD Biquad Filter Control Register 2 0x0000_0000 BIQEN Reserved Reserved BIQB2 BIQB2 Bits Description VAD Biquad Filter Enable Bit [31] BIQEN 0 = VAD Biquad Filter Disabled.
  • Page 891 ISD94100 Series Technical Reference Manual VAD Control Register 0 (VAD_CTL0) Register Offset R/W Description Reset Value VAD_CTL0 VAD_BA+0x10 R/W VAD Control Register 0 0x0007_00CC Reserved Reserved LTAT Reserved STAT Bits Description Reserved. Any values read should be ignored. When writing to this field always write [31:20] Reserved with reset value.
  • Page 892 ISD94100 Series Technical Reference Manual VAD Control Register 1 (VAD_CTL1) Register Offset R/W Description Reset Value VAD_CTL1 VAD_BA+0x14 R/W VAD Control Register 1 0x0000_7FFF STTHRELWM STTHRELWM STTHREHWM STTHREHWM Bits Description Short Term Power Threshold Lower Limit [31:16] STTHRELWM To check if the incoming signal is small enough so that VAD status can be terminated. Short Term Power Threshold Upper Limit [15:0] STTHREHWM...
  • Page 893 ISD94100 Series Technical Reference Manual VAD Control Register 2 (VAD_CTL2) Register Offset R/W Description Reset Value VAD_CTL2 VAD_BA+0x18 R/W VAD Control Register 2 0x0000_0000 LTTHRE LTTHRE Reserved Reserved Bits Description Long Term Power Threshold To check the background energy, also serve as the lower limit of long term power. When [31:16] LTTHRE the long term power value is lower than the threshold, it will be set to the threshold value...
  • Page 894 ISD94100 Series Technical Reference Manual VAD Control Register 3 (VAD_CTL3) Register Offset R/W Description Reset Value VAD_CTL3 VAD_BA+0x1C R/W VAD Control Register 3 0x0000_7FFF DEVTHRE DEVTHRE Bits Description Hang Over time Hang Over time setting, means how many clocks (CLKSD) of the ACTIVE [31:16] (VAD_STATUS0[31]) staying high when the calculation is no longer bigger than the threshold...
  • Page 895 ISD94100 Series Technical Reference Manual VAD Status Register 0 (VAD_STATUS0) Register Offset R/W Description Reset Value VAD_STATUS0 VAD_BA+0x20 VAD Status Read-Back Register 0 0x0000_0000 ACTIVE Reserved Reserved Bits Description VAD Activation Flag (Read Only) When the voice active event occurs, this bit will be set to 1. 0 = No effect.
  • Page 896 ISD94100 Series Technical Reference Manual VAD Status Register 1 (VAD_STATUS1) Register Offset R/W Description Reset Value VAD_STATUS1 VAD_BA+0x24 VAD Status Read-Back Register 1 0x0000_0000 Bits Description Long Term Signal Power (Read Only) [31:16] This field shows the long term signal power value. Deviation (Read Only) [15:0] This field shows deviation of the Long Term Signal Power and Short Term Signal Power.

  • Page 897: Audio Dpwm Modulator (Dpwm)

    ISD94100 Series Technical Reference Manual 6.21 Audio DPWM Modulator (DPWM) 6.21.1 Overview The DPWM modulator is sigma-delta modulator which is for class D amplifer. ISD94100 series has 3 DPWM modulator and each one can provide 2 differential pins. 6.21.2 Features ...

  • Page 898: Functional Description

    ISD94100 Series Technical Reference Manual PD.0 MFP5 PA.5 MFP3 DPWM_LP PC.13 MFP3 PD.1 MFP5 PA.10 MFP3 DPWM_RN PC.10 MFP3 PD.5 MFP5 PA.11 MFP3 DPWM_RP PC.11 MFP3 PD.6 MFP5 PA.13 MFP3 DPWM_SN PC.14 MFP3 PD.8 MFP5 PA.14 MFP3 DPWM_SP PC.15 MFP3 PD.9 MFP5 6.21.5 Functional Description...

  • Page 899: Figure 6.21-2 Dpwm Clock Control Diagram

    ISD94100 Series Technical Reference Manual Figure 6.21-2 DPWM Clock Control Diagram 6.21.5.2 Determining Sample Rate The sample rate at which the DPWM block consumes audio data is given by: Fs = F_DPWM_CLK / ( ZOHDIV * K) K = 125, if CLKSET(DPWM_CTL[31]) is 1. K = 128, if CLKSET(DPWM_CTL[31]) is 0.
  • Page 900 ISD94100 Series Technical Reference Manual b0 = norm b1 = -2 *b0 b2 = b0 a1 = 2*(TK^2-1)*norm a2 = (1-TK/Q +TK^2) * norm C. Second order bandpass filter coefficient b0 = TK/Q *norm b1 = 0 b2 = -b0 a1 = 2*(TK^2-1)*norm a2 = (1-TK/Q +TK^2) * norm D.
  • Page 901 ISD94100 Series Technical Reference Manual b1_1 = 2 *b0 b2_1 = b0 a1_1 = 2*(TK^2-1)*norm a2_1 = (1-TK/Q T+K^2) * norm b0_2=T K^2 *norm b1_2 = 2 *b0 b2_2 = b0 a1_2 = 2*(TK^2-1)*norm a2_2 = (1-TK/Q +TK^2) * norm b0_3 = norm b1_3 = -2 *b0 b2_3 = b0...

  • Page 902: Figure 6.21-3 Splitter Frequency Response And Channel Distribution

    ISD94100 Series Technical Reference Manual separation for left and right channels. Left and right channels keep high frequency signals and the low frequency signals go to sub-woofer. Figure 6.21-3 Splitter Frequency Response and Channel Distribution 6.21.5.5 Biquad Filter Configuring A coefficient programmable 10 bands biquad filter (20 -Order IIR filter) is available.

  • Page 903: Figure 6.21-4 Audio Dpwm Fifo Contents For Various Data Width

    ISD94100 Series Technical Reference Manual To configure the biquad filter and splitter: Reset audio DPWM modulator by setting register DPWMRST (SYS_IPRST2[6]).   Enable coefficient programming mode setting register PRGCOEFF (DPWM_COEFFCTL[0]) to “1”.  Set coefficients in coefficient registers, biquad coefficient is first, last 4 band coefficients are for splitter.
  • Page 904 ISD94100 Series Technical Reference Manual 6.21.5.8 Peripheral DMA Request Normal use of the audio DPWM is with PDMA. In this mode DPWM requests PDMA service whenever there is space in FIFO. PDMA channel will copy data from a streaming buffer to the DPWM FIFO and alert the CPU when buffer is empty.

  • Page 905: Register Map

    ISD94100 Series Technical Reference Manual 6.21.6 Register Map R: read only, W: write only, R/W: both read and write. Register Offset R/W Description Reset Value DPWM Base Address: DPWM_BA = 0x4006_4000 DPWM_CTL DPWM_BA+0x00 R/W DPWM Control Register 0x0000_0600 DPWM_STATUS DPWM_BA+0x04 DPWM Status Register 0x0000_0002 DPWM_PDMACTL...
  • Page 906 ISD94100 Series Technical Reference Manual Register Offset R/W Description Reset Value DPWM Base Address: DPWM_BA = 0x4006_4000 Coefficient a2 Transfer function for band 2 DPWM_COEFF9 DPWM_BA+0x124 fixed point – 3.21 format 0x0000_0000 floating point – single precision point Coefficient b0 Transfer function for band 3 DPWM_COEFF10 DPWM_BA+0x128 fixed point –...
  • Page 907 ISD94100 Series Technical Reference Manual Register Offset R/W Description Reset Value DPWM Base Address: DPWM_BA = 0x4006_4000 Coefficient b2 Transfer function for band 5 DPWM_COEFF22 DPWM_BA+0x158 fixed point – 3.21 format 0x0000_0000 floating point – single precision point Coefficient a1 Transfer function for band 5 DPWM_COEFF23 DPWM_BA+0x15C fixed point –...
  • Page 908 ISD94100 Series Technical Reference Manual Register Offset R/W Description Reset Value DPWM Base Address: DPWM_BA = 0x4006_4000 Coefficient b0 Transfer function for band 8 DPWM_COEFF35 DPWM_BA+0x18C fixed point – 3.21 format 0x0000_0000 floating point – single precision point Coefficient b1 Transfer function for band 8 DPWM_COEFF36 DPWM_BA+0x190 fixed point –...
  • Page 909 ISD94100 Series Technical Reference Manual Register Offset R/W Description Reset Value DPWM Base Address: DPWM_BA = 0x4006_4000 Coefficient a1 Transfer function for band 10 DPWM_COEFF48 DPWM_BA+0x1C0 fixed point – 3.21 format 0x0000_0000 floating point – single precision point Coefficient a2 Transfer function for band 10 DPWM_COEFF49 DPWM_BA+0x1C4 fixed point –...

  • Page 910: Register Description

    ISD94100 Series Technical Reference Manual 6.21.7 Register Description DPWM Control Register (DPWM_CTL) Register Offset R/W Description Reset Value DPWM_CTL DPWM_BA+0x00 R/W DPWM Control Register 0x0000_0600 CLKSET Reserved FCLR BIQBANDNUM Reserved SPLTON BIQON FLTEN FLTINTBIT THIE Reserved DRVEN DPWMEN Reserved DEADTIME Reserved FIFOWIDTH Bits...
  • Page 911 ISD94100 Series Technical Reference Manual BIQ Enable Bit [21] BIQON 0 = Biquad filter Disabled. 1 = Biquad filter Enabled. Floating Point Format Enable Bit [20] FLTEN 0 = Input data is fixed point. 1 = Input data is single precision point. Floating Integer Bits Setting 000 = Integer is 0, Data range +/- 0.999.
  • Page 912 ISD94100 Series Technical Reference Manual DPWM Status Register (DPWM_STATUS) Register Offset R/W Description Reset Value DPWM_STATUS DPWM_BA+0x04 DPWM Status Register 0x0000_0002 Reserved Reserved Reserved FIFOPTR FIFOPTR Reserved THIF EMPTY FULL Bits Description Reserved. Any values read should be ignored. When writing to this field always write with [31:9] Reserved reset value.
  • Page 913 ISD94100 Series Technical Reference Manual DPWM PDMA Control Register (DPWM_PDMACTL) Register Offset R/W Description Reset Value DPWM_PDMACTL DPWM_BA+0x08 R/W DPWM PDMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDMAEN Bits Description Reserved. Any values read should be ignored. When writing to this field always write with [31:1] Reserved reset value.
  • Page 914 ISD94100 Series Technical Reference Manual DPWM FIFO Data Input Register (DPWM_FIFO) Register Offset R/W Description Reset Value DPWM_FIFO DPWM_BA+0x0C DPWM FIFO Data Input Register 0x0000_0000 FIFO FIFO FIFO FIFO Bits Description FIFO Data Input Register DPWM contains 32 words (32x32 bit) data buffer for data transmit. A write to this register FIFO [31:0] pushes data onto the FIFO data buffer and increments the write pointer.
  • Page 915 ISD94100 Series Technical Reference Manual DPWM Zero Order Hold Division Register (DPWM_ZOHDIV) Register Offset R/W Description Reset Value DPWM_ZOHDIV DPWM_BA+0x10 R/W DPWM Zero Order Hold Division Register 0x0000_0804 Reserved Reserved CLKDIV CLKDIV ZOHDIV Bits Description Reserved. Any values read should be ignored. When writing to this field always write with [31:19] Reserved reset value.
  • Page 916 ISD94100 Series Technical Reference Manual DPWM Output Signal Frequency Control Register (DPWM_FREQ) Register Offset R/W Description Reset Value DPWM_FREQ DPWM_BA+0x14 R/W DPWM Output Signal Frequency Control Register 0x0000_0000 Reserved Reserved Reserved STEPSEL Reserved FREQSEL Bits Description Reserved. Any values read should be ignored. When writing to this field always write with [31:11] Reserved reset value.
  • Page 917 ISD94100 Series Technical Reference Manual DPWM Coefficient Control Register (DPWM_COEFFCTL) Register Offset R/W Description Reset Value DPWM_COEFFCTL DPWM_BA+0xFC R/W BIQ Coefficient Control 0x0000_0000 Reserved Reserved Reserved Reserved COEFFFLTEN PRGCOEFF Bits Description Reserved. Any values read should be ignored. When writing to this field always write with [31:2] Reserved reset value.
  • Page 918 ISD94100 Series Technical Reference Manual DPWM Coefficient Register (DPWM_COEFFn) Register Offset Description Reset Value DPWM_COEFF0 DPWM_BA+0x100 R/W Coefficient b0 Transfer function for band 1 0x0000_0000 fixed point – 3.21 format floating point – single precision point DPWM_COEFF1 DPWM_BA+0x104 R/W Coefficient b1 Transfer function for band 1 0x0000_0000 fixed point –...
  • Page 919 ISD94100 Series Technical Reference Manual fixed point – 3.21 format floating point – single precision point DPWM_COEFF14 DPWM_BA+0x138 R/W Coefficient a2 Transfer function for band 3 0x0000_0000 fixed point – 3.21 format floating point – single precision point DPWM_COEFF15 DPWM_BA+0x13C R/W Coefficient b0 Transfer function for band 4 0x0000_0000 fixed point –...
  • Page 920 ISD94100 Series Technical Reference Manual floating point – single precision point DPWM_COEFF28 DPWM_BA+0x170 R/W Coefficient a1 Transfer function for band 6 0x0000_0000 fixed point – 3.21 format floating point – single precision point DPWM_COEFF29 DPWM_BA+0x174 R/W Coefficient a2 Transfer function for band 6 0x0000_0000 fixed point –...
  • Page 921 ISD94100 Series Technical Reference Manual floating point – single precision point DPWM_COEFF42 DPWM_BA+0x1A8 R/W Coefficient b2 Transfer function for band 9 0x0000_0000 fixed point – 3.21 format floating point – single precision point DPWM_COEFF43 DPWM_BA+0x1AC R/W Coefficient a1 Transfer function for band 9 0x0000_0000 fixed point –...

  • Page 922: Electrical Characteristics

    ISD94100 Series Technical Reference Manual ELECTRICAL CHARACTERISTICS ® For information on ISD94100 series electrical characteristics, please refer to ISD Cortex -M4 Chipcorder ISD94100 series Datasheet. Sep 9, 2019 Page 922 of 928 Rev1.09...

  • Page 923: Application Circuit

    ISD94100 Series Technical Reference Manual APPLICATION CIRCUIT USB_VBUS USB_D- USB Slot USB_D+ 1 uF 0.1uF Power SPI_SS SPI Device SPI_CLK SPI_MISO MISO 1 uF 0.1uF SPI_MOSI MOSI 4.7K 4.7K ICE_CLK I2C_SCL ICE_DAT C Device Interface I2C_SDA PC COM Port RS 232 Transceiver ROUT UART Reset...

  • Page 924: Package Dimensions

    ISD94100 Series Technical Reference Manual PACKAGE DIMENSIONS QFN 48L (6x6x0.8 mm Pitch 0.4 mm) Sep 9, 2019 Page 924 of 928 Rev1.09...

  • Page 925: Lqfp 64L (7X7X1.4 Mm Footprint 2.0 Mm)

    ISD94100 Series Technical Reference Manual LQFP 64L (7x7x1.4 mm footprint 2.0 mm) Sep 9, 2019 Page 925 of 928 Rev1.09...

  • Page 926: Lqfp 64L (10X10X1.4 Mm Footprint 2.0 Mm)

    ISD94100 Series Technical Reference Manual LQFP 64L (10x10x1.4 mm footprint 2.0 mm) Sep 9, 2019 Page 926 of 928 Rev1.09...

  • Page 927: Revision History

    ISD94100 Series Technical Reference Manual 10 REVISION HISTORY Date Revision Description 2017.10.27 1. Preliminary version 1. Section 6.2.4 updated. 2. The description of register RWENF updated. 3. Added EADC_CHSPC register. 2017.12.22 1.01 4. Added Section 6.16.5.16. 5. Section 6.19, 6.20 and 6.21 updated. 6.
  • Page 928 ISD94100 Series Technical Reference Manual Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

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