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ISD94124BYI
Nuvoton ISD94124BYI Manuals
Manuals and User Guides for Nuvoton ISD94124BYI. We have
1
Nuvoton ISD94124BYI manual available for free PDF download: Technical Reference Manual
Nuvoton ISD94124BYI Technical Reference Manual (928 pages)
ISD ARM Cortex-M4F SoC
Brand:
Nuvoton
| Category:
Single board computers
| Size: 8.23 MB
Table of Contents
Table of Contents
2
1 General Description
18
2 Features
19
ISD94100 Series Features
19
3 Abbreviations
26
Table 3.1-1 List of Abbreviations
27
4 Parts Information List and Pin Configuration
28
Parts Information
28
Table 4.1-1 Devices Features and Peripheral Counts
28
Ordering Information
29
Figure 4.2-1 Ordering Information Scheme
29
Table 4.2-1 Devices Features Summary
30
Pin Configuration
31
QFN48 (6X6 MM) Pin Diagram
31
Figure 4.3-1 QFN48 (6X6 MM) Pin Diagram
31
LQFP64 (7X7 MM) Pin Diagram
32
Figure 4.3-2 LQFP64 (7X7 MM) Pin Diagram
32
LQFP64 (10X10 MM) Pin Diagram
33
Figure 4.3-3 LQFP64 (10X10 MM) Pin Diagram
33
Pin Description
34
Table 4.4-1 Pin Description
42
GPIO Alternate Function Summary
43
Table 4.5-1 GPIO Alternate Function Summary
44
5 Block Diagram
45
ISD94100 Series Block Diagram
45
Figure 5.1-1 ISD94100 Series Block Diagram
45
6 Functional Description
46
ARM ® Cortex ® -M4 Core
46
Figure 6.1-1 Cortex ® -M4 Block Diagram
46
System Manager
49
Overview
49
System Reset
49
Figure 6.2-1 System Reset Sources
50
Figure 6.2-2 Nreset Reset Waveform
51
Table 6.2.2-1 Reset Value of Registers
51
Figure 6.2-3 Brown-Out Detector (BOD) Waveform
52
System Power Distribution
53
Table 6.2.2-2 Reset Flag Table
53
Power Modes
54
Figure 6.2-4 ISD94100 Series Power Distribution Diagram
54
Power Modes Settings and Wake-Up Sources
56
Table 6.2.5-1 Power Mode Table
56
Figure 6.2-5 ISD94100 Series Power Mode State Machine
57
Table 6.2.5-2 Power Mode Difference Table
57
Table 6.2.5-3 Power Mode Difference Table
57
Table 6.2.5-4 Clocks in Power Modes
58
Table 6.2.5-5 Re-Entering Power-Down Mode Condition
60
Brown-Out Detector and Low Voltage Reset Controller Configuration
61
Table 6.2.6-1 Brown-Out Detector and Low Voltage Reset Controller Effect Table
61
System Memory Map
62
SRAM Memory Organization
63
Figure 6.2-6 SRAM Block Diagram
63
Table 6.2.7-1 Address Space Assignments for On-Chip Controllers
63
HIRC Auto Trim
64
Figure 6.2-7 SRAM Memory Organization
64
Register Map
66
Register Description
67
System Timer (Systick)
98
Nested Vectored Interrupt Controller (NVIC)
102
Table 6.2.13-1 Exception Model
103
Table 6.2.13-2 Interrupt Number Table
104
System Control Register
131
Table 6.2.14-1 Priority Grouping
135
Clock Controller
140
Overview
140
Figure 6.3-1 Clock Generator Global View Diagram
141
Clock Generator
142
Figure 6.3-2 Clock Generator Block Diagram
142
System Clock and Systick Clock
143
Figure 6.3-3 System Clock Block Diagram
143
Figure 6.3-4 HXT Stop Protect Procedure
144
Figure 6.3-5 Systick Clock Control Block Diagram
144
Peripheral Clock
145
Power-Down Mode Clock
145
Clock Output
145
Figure 6.3-6 Clock Output Block Diagram
145
Clock Setting Limitation
146
Register Map
147
Register Description
149
Table 6.3.9-1 the Symbol Definition of PLL Output Frequency Formula
167
Flash Memory Controller (FMC)
191
Overview
191
Features
191
Block Diagram
192
Figure 6.4-1 Flash Memory Controller Block Diagram
192
Functional Description
194
Figure 6.4-2 Memory Organization
194
Figure 6.4-3 Data Flash Shared with 512 KB APRM Example
194
Table 6.4.4-1 Flash Memory Address Map
195
Figure 6.4-4 Boot from LDROM with IAP Support
196
Table 6.4.4-2 Boot Configuration
196
Figure 6.4-5 Boot from APROM with IAP Support
197
Figure 6.4-6 Boot from LDROM Without IAP Support
198
Figure 6.4-7 Boot from APROM Without IAP Support
198
Figure 6.4-8 ISP Procedure Example
201
Table 6.4.4-3 ISP Command List
201
Table 6.4.4-4 FMC Control Registers for Flash Read/Write
202
Figure 6.4-9 Flash 32-Bit Write Procedure
203
Figure 6.4-10 Flash 64-Bit Write Procedure
204
Figure 6.4-11 Timeline Comparison for Write Operations
205
Figure 6.4-12 Firmware in SRAM for Multi-Word Programming
205
Figure 6.4-13 Multi-Word Programming Flow Chart
207
Figure 6.4-14 Fast Flash Programming Verification Flow
208
Figure 6.4-15 Verification Flow
209
Figure 6.4-16 Flash CRC32 Checksum Calculation
209
Table 6.4.4-5 Flash Access Optimized Cycle under Auto-Tuning Function
212
Figure 6.4-17 Flash Access Cycle Auto-Tuning Flow
213
Table 6.4.4-6 the Lock Effect Table with Two Protections
214
Register Map
215
Register Description
217
General Purpose I/O (GPIO)
240
Overview
240
Features
240
Block Diagram
240
Basic Configuration
241
Figure 6.5-1 GPIO Controller Block Diagram
241
Functional Description
242
Figure 6.5-2 Push-Pull Output
242
Figure 6.5-3 Open-Drain Output
243
Figure 6.5-4 Quasi-Bidirectional I/O Mode
243
Figure 6.5-5 GPIO Rising Edge Trigger Interrupt
244
Figure 6.5-6 GPIO Falling Edge Trigger Interrupt
245
Table 6.5.5-1 De-Bounce Function Setting Table
245
Register Map
246
Register Description
248
PDMA Controller (PDMA)
264
Overview
264
Features
264
Block Diagram
264
Figure 6.6-1 PDMA Controller Block Diagram
264
Basic Configuration
265
Functional Description
265
Figure 6.6-2 Descriptor Table Entry Structure
265
Table 6.6.5-1 Channel Priority Table
266
Figure 6.6-3 Basic Mode Finite State Machine
267
Figure 6.6-4 Descriptor Table Link List Structure
268
Figure 6.6-5 Scatter-Gather Mode Finite State Machine
268
Figure 6.6-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode
270
Figure 6.6-7 Example of PDMA Channel 0 Time-Out Counter Operation
271
Figure 6.6-8 Stride Function Block Transfer
271
Register Map
273
Register Description
278
Timer Controller (TMR)
338
Overview
338
Features
338
Block Diagram
340
Figure 6.7-1 Timer Controller Block Diagram
340
Figure 6.7-2 Clock Source of Timer Controller
341
Figure 6.7-3 PWM Generator Overview Block Diagram
342
Figure 6.7-4 PWM System Clock Source Control
342
Figure 6.7-5 PWM Counter Clock Source Control
343
Figure 6.7-6 PWM Independent Mode Architecture Diagram
343
Basic Configuration
344
Figure 6.7-7 PWM Complementary Mode Architecture Diagram
344
Timer Functional Description
345
Figure 6.7-8 Continuous Counting Mode
347
Figure 6.7-9 External Capture Mode
348
Figure 6.7-10 External Reset Counter Mode
348
Figure 6.7-11 Internal Timer Trigger
349
PWM Functional Description
350
Figure 6.7-12 Inter-Timer Trigger Capture Timing
350
Figure 6.7-13 PWM Prescale Waveform in up Count Type
351
Figure 6.7-14 PWM up Count Type
351
Figure 6.7-15 PWM down Count Type
352
Figure 6.7-16 PWM Up-Down Count Type
352
Figure 6.7-17 PWM Comparator Events in Up-Down Count Type
353
Figure 6.7-18 Period Loading Mode with up Count Type
354
Figure 6.7-19 Immediately Loading Mode with up Count Type
355
Figure 6.7-20 PWM Pulse Generation in Up-Down Count Type
355
Figure 6.7-21 PWM Pulse Generation in up Count Type
356
Figure 6.7-22 PWM Pulse Generation in down Count Type
356
Table 6.7.6-1 PWM Pulse Generation Event Priority in up Count Type
356
Figure 6.7-23 PWM 0% to 100% Duty Cycle in up Count Type and Up-Down Count Type
357
Table 6.7.6-2 PWM Pulse Generation Event Priority in down Count Type
357
Table 6.7.6-3 PWM Pulse Generation Event Priority in Up-Down Count Type
357
Figure 6.7-24 PWM Independent Mode Output Waveform
358
Figure 6.7-25 PWM Complementary Mode Output Waveform
358
Figure 6.7-26 Pwmx_Ch0 Output Control in Independent Mode
358
Figure 6.7-27 Pwmx_Ch0 and Pwmx_Ch1 Output Control in Complementary Mode
359
Figure 6.7-28 Dead-Time Insertion
359
Figure 6.7-29 PWM Output Mask Control Waveform
360
Figure 6.7-30 Pwmx_Ch0 and Pwmx_Ch1 Polarity Control with Dead-Time Insertion
361
Figure 6.7-31 PWM Interrupt Architecture Diagram
362
Figure 6.7-32 PWM Trigger ADC Block Diagram
362
Register Map
363
Register Description
368
PWM Generator and Capture Timer (PWM)
402
Overview
402
Features
402
Block Diagram
404
Figure 6.8-1 PWM Generator Overview Block Diagram
404
Figure 6.8-2 PWM System Clock Source Control
404
Figure 6.8-3 PWM Clock Source Control
405
Table 6.8.3-1 PWM System Clock Source Control Registers Setting Table
405
Figure 6.8-4 PWM Independent Mode Architecture Diagram
406
Basic Configuration
407
Figure 6.8-5 PWM Complementary Mode Architecture Diagram
407
Functional Description
408
Figure 6.8-6 PWM0_CH0 Prescaler Waveform in up Counter Type
408
Figure 6.8-7 PWM0 Counter Waveform When Set Clear Counter
409
Figure 6.8-8 PWM up Counter Type
409
Figure 6.8-9 PWM down Counter Type
410
Figure 6.8-10 PWM Up-Down Counter Type
411
Figure 6.8-11 PWM Compared Point Events in Up-Down Counter Type
412
Figure 6.8-12 PWM Double Buffering Illustration
413
Figure 6.8-13 Period Loading in Up-Count Mode
414
Figure 6.8-14 Immediately Loading in Up-Count Mode
415
Figure 6.8-15 Window Loading in Up-Count Mode
416
Figure 6.8-16 Center Loading in Up-Down-Count Mode
417
Figure 6.8-17 PWM One-Shot Mode Output Waveform
418
Figure 6.8-18 PWM Pulse Generation
419
Figure 6.8-19 PWM 0% to 100% Pulse Generation
419
Table 6.8.5-1 PWM Pulse Generation Event Priority for Up-Counter
419
Table 6.8.5-2 PWM Pulse Generation Event Priority for Down-Counter
420
Table 6.8.5-3 PWM Pulse Generation Event Priority for Up-Down-Counter
420
Figure 6.8-20 PWM Independent Mode Waveform
421
Figure 6.8-21 PWM Complementary Mode Waveform
421
Figure 6.8-22 PWM Group Function Waveform
422
Figure 6.8-23 PWM SYNC_IN Noise Filter Block Diagram
423
Figure 6.8-24 PWM Counter Synchronous Function Block Diagram
424
Figure 6.8-25 PWM Synchronous Function with Synchronize Source from SYNC_IN Signal
425
Figure 6.8-26 PWM0_CH0 Output Control in Independent Mode
425
Figure 6.8-27 PWM0_CH0 and PWM0_CH1 Output Control in Complementary Mode
426
Figure 6.8-28 Dead-Time Insertion
427
Figure 6.8-29 Illustration of Mask Control Waveform
427
Figure 6.8-30 Brake Noise Filter Block Diagram
428
Figure 6.8-31 Brake Block Diagram for PWM0_CH0 and PWM0_CH1 Pair
429
Figure 6.8-32 Edge Detector Waveform for PWM0_CH0 and PWM0_CH1 Pair
430
Figure 6.8-33 Level Detector Waveform for PWM0_CH0 and PWM0_CH1 Pair
430
Figure 6.8-34 Brake Source Block Diagram
431
Figure 6.8-35 Brake System Fail Block Diagram
431
Figure 6.8-36 Initial State and Polarity Control with Rising Edge Dead-Time Insertion
432
Figure 6.8-37 PWM0_CH0 and PWM0_CH1 Pair Interrupt Architecture Diagram
433
Figure 6.8-38 PWM0_CH0 and PWM0_CH1 Pair Trigger EADC Block Diagram
434
Figure 6.8-39 PWM Trigger EADC in Up-Down Counter Type Timing Waveform
434
Figure 6.8-40 PWM0_CH0 Capture Block Diagram
435
Figure 6.8-41 Capture Operation Waveform
436
Figure 6.8-42 Capture PDMA Operation Waveform of Channel 0
438
Register Map
439
Register Description
443
Watchdog Timer (WDT)
525
Overview
525
Features
525
Block Diagram
525
Basic Configuration
525
Figure 6.9-1 Watchdog Timer Block Diagram
525
Functional Description
526
Figure 6.9-2 Watchdog Timer Clock Control
526
Figure 6.9-3 Watchdog Timer Time-Out Interval and Reset Period Timing
527
Table 6.9.5-1 Watchdog Timer Time-Out Interval Period Selection
527
Register Map
529
Register Description
530
Window Watchdog Timer (WWDT)
533
Overview
533
Features
533
Block Diagram
533
Figure 6.10-1 WWDT Block Diagram
533
Basic Configuration
534
Functional Description
534
Figure 6.10-2 WWDT Clock Control
534
Figure 6.10-3 WWDT Reset and Reload Behavior
535
Table 6.10.5-1 WWDT Prescaler Value Selection
535
Figure 6.10-4 WWDT Reload Counter When CNTDAT > CMPDAT
536
Figure 6.10-5 WWDT Reload Counter When WWDT_CNT < WINCMP
537
Figure 6.10-6 WWDT Interrupt and Reset Signals
537
Table 6.10.5-2 CMPDAT Setting Limitation
537
Register Map
538
Register Description
539
Real Time Clock (RTC)
544
Overview
544
Features
544
Block Diagram
545
Basic Configuration
545
Functional Description
545
Figure 6.11-1 RTC Block Diagram
545
Table 6.11.5-1 RTC Read/Write Enable
546
Table 6.11.5-2 12/24 Hour Time Scale Selection
547
Table 6.11.5-3 Registers Value after Power-On
548
Register Map
549
Register Description
550
UART Interface Controller (UART)
566
Overview
566
Features
566
Block Diagram
567
Figure 6.12-1 UART Clock Control Diagram
567
Table 6.12.2-1 UART Feature
567
Figure 6.12-2 UART Block Diagram
568
Basic Configuration
570
Table 6.12.3-1 UART Interrupt
570
Functional Description
571
Table 6.12.4-1 UART Interface Controller Pin
571
Table 6.12.5-1 UART Controller Baud Rate Equation Table
571
Table 6.12.5-2 UART Controller Baud Rate Parameter Setting Example Table
572
Table 6.12.5-3 UART Controller Baud Rate Register Setting Example Table
572
Table 6.12.5-4 Baud Rate Compensation Example Table 1
573
Table 6.12.5-5 Baud Rate Compensation Example Table 2
573
Figure 6.12-3 Auto-Baud Rate Measurement
574
Figure 6.12-4 Transmit Delay Time Operation
575
Figure 6.12-5 UART Ncts Wake-Up Case1
576
Figure 6.12-6 UART Ncts Wake-Up Case2
576
Figure 6.12-7 UART Data Wake-Up
577
Figure 6.12-8 UART RX FIFO Reached Threshold Wake-Up
577
Figure 6.12-9 UART RS-485 AAD Mode Address Match Wake-Up
578
Figure 6.12-10 UART RX FIFO Threshold Time-Out Wake-Up
578
Table 6.12.5-6 UART Controller Interrupt Source and Flag List
580
Table 6.12.5-7 UART Line Control of Word and Stop Length Setting
581
Table 6.12.5-8 UART Line Control of Parity Bit Setting
581
Figure 6.12-11 Auto-Flow Control Block Diagram
582
Figure 6.12-12 UART Ncts Auto-Flow Control Enabled
583
Figure 6.12-13 UART Nrts Auto-Flow Control Enabled
583
Figure 6.12-14 UART Nrts Auto-Flow with Software Control
584
Figure 6.12-15 RS-485 Nrts Driving Level in Auto Direction Mode
586
Figure 6.12-16 RS-485 Nrts Driving Level with Software Control
586
Figure 6.12-17 Structure of RS-485 Frame
587
Register Map
588
Register Description
589
I 2 C Serial Interface Controller (I 2 C)
617
Overview
617
Features
617
Block Diagram
617
Basic Configuration
618
Figure 6.13-1 I 2 C Controller Block Diagram
618
Functional Description
619
Figure 6.13-2 I2C Bus Timing
620
Figure 6.13-3 I 2 C Protocol
620
Figure 6.13-4 Bit Transfer on the I C Bus
621
Figure 6.13-5 Acknowledge on the I C Bus
621
Figure 6.13-6 Bit Transfer on the I C Bus
622
Figure 6.13-7 Acknowledge on the I C Bus
623
Figure 6.13-8 Master Transmits Data to Slave by 7-Bit
623
Figure 6.13-9 Master Reads Data from Slave by 7-Bit
623
Figure 6.13-10 Master Transmits Data to Slave by 10-Bit
624
Figure 6.13-11 Master Reads Data from Slave by 10-Bit
624
Figure 6.13-12 Control I
625
Status
625
Figure 6.13-13 Master Transmitter Mode Control Flow
627
Figure 6.13-14 Master Receiver Mode Control Flow
629
Figure 6.13-15 Slave Mode Control Flow
631
Figure 6.13-16 GC Mode
634
Figure 6.13-17 Arbitration Lost
636
Table 6.13.5-1 Reserved Smbus Address
637
Figure 6.13-18 Bus Management Packet Protocol Diagram Element Key
638
Figure 6.13-19 7-Bit Addressable Device to Host Communication
639
Figure 6.13-20 7-Bit Addressable Device Responds to an ARA
639
Figure 6.13-21 Bus Management ALERT Function
640
Figure 6.13-22 Bus Management Time out Timing
641
Figure 6.13-23 Bus Clock Low Time out Timing
641
Table 6.13.5-2 Relationship between I
642
Baud Rate and PCLK
642
Figure 6.13-24 Setup Time Wrong Adjustment
643
Figure 6.13-25 Hold Time Wrong Adjustment
643
Figure 6.13-26 I 2 C Data Shifting Direction
644
Table 6.13.5-3 I 2 C Status Code Description
645
Figure 6.13-27 I 2 C Time-Out Count Block Diagram
646
Figure 6.13-28 I 2 C Wake-Up Related Signals Waveform
647
Figure 6.13-29 EEPROM Random Read
648
Figure 6.13-30 Protocol of EEPROM Random Read
649
Register Map
650
Register Description
652
Serial Peripheral Interface (SPI)
674
Overview
674
Features
674
Table 6.14.2-1 SPI Feature Difference (SPI0~SPI2)
675
Block Diagram
676
Figure 6.14-1 SPI Block Diagram (SPI0)
676
Figure 6.14-2 SPI Block Diagram (SPI1/2)
676
Basic Configuration
678
Functional Description
680
Figure 6.14-4 SPI Peripheral Clock
680
Figure 6.14-5 SPI0 Full-Duplex Master Mode Application Block Diagram
681
Figure 6.14-6 SPI0 Full-Duplex Slave Mode Application Block Diagram
681
Figure 6.14-7 SPI1 ~ SPI2 Full-Duplex Master Mode Application Block Diagram
682
Figure 6.14-8 SPI1 ~ SPI2 Full-Duplex Slave Mode Application Block Diagram
682
Figure 6.14-9 32-Bit in One Transaction
683
Figure 6.14-10 Automatic Slave Selection (SSACTPOL = 0, SUSPITV > 0X2)
684
Figure 6.14-11 Automatic Slave Selection (SSACTPOL = 0, SUSPITV < 0X3)
685
Figure 6.14-12 Byte Reorder Function
686
Figure 6.14-13 Timing Waveform for Byte Suspend
686
Figure 6.14-14 SPI Half-Duplex Master Mode Application Block Diagram
687
Figure 6.14-15 SPI Half-Duplex Slave Mode Application Block Diagram
687
Figure 6.14-16 Two-Bit Transfer Mode System Architecture
689
Figure 6.14-17 Two-Bit Transfer Mode Timing (Master Mode)
689
Figure 6.14-18 Bit Sequence of Dual Output Mode
690
Figure 6.14-19 Bit Sequence of Dual Input Mode
690
Figure 6.14-20 Bit Sequence of Quad Output Mode
691
Figure 6.14-21 Bit Sequence of Quad Input Mode
692
Figure 6.14-22 FIFO Threshold Comparator
693
Figure 6.14-23 Transmit FIFO Buffer Example
694
Figure 6.14-24 Receive FIFO Buffer Example
695
Figure 6.14-25 TX Underflow Event and Slave under Run Event
696
Figure 6.14-26 Two-Bit Transfer Mode FIFO Buffer Example (SPI0 Only)
696
Figure 6.14-27 TX Underflow Event (SPI0 Slave 3-Wire Mode Enabled)
696
Figure 6.14-28 Slave Mode Bit Count Error
697
Figure 6.14-29 Slave Time-Out Event (for SPI0)
697
Figure 6.14-30 I 2 S Data Format Timing Diagram
700
Figure 6.14-31 MSB Justified Data Format Timing Diagram
701
Figure 6.14-32 PCM Mode a Timing Diagram
701
Figure 6.14-33 PCM Mode B Timing Diagram
701
Timing Diagram
704
Figure 6.14-34 FIFO Contents for Various I S Modes
704
Figure 6.14-35 SPI Timing in Master Mode
704
Figure 6.14-36 SPI Timing in Master Mode (Alternate Phase of Spix_Clk)
705
Figure 6.14-37 SPI Timing in Slave Mode
705
Figure 6.14-38 SPI Timing in Slave Mode (Alternate Phase of Spix_Clk)
705
Programming Examples
706
Register Map
708
Register Description
710
CRC Controller (CRC)
746
Overview
746
Features
746
Block Diagram
747
Basic Configuration
747
Functional Description
747
Figure 6.15-1 CRC Generator Block Diagram
747
Figure 6.15-2 CHECKSUM Bit Order Reverse Functional Block
748
Figure 6.15-3 Write Data Bit Order Reverse Functional Block
748
Register Map
749
Register Description
750
Enhanced 12-Bit Analog-To-Digital Converter (EADC)
755
Overview
755
Features
755
Block Diagram
756
Basic Configuration
756
Figure 6.16-1 ADC Converter Block Diagram
756
Functional Description
757
Figure 6.16-2 Sample Module 0~3 Block Diagram
758
Figure 6.16-3 Sample Module 4~12 Block Diagram
759
Figure 6.16-4 EADC Clock Control
760
Figure 6.16-5 Example ADC Conversion Timing Diagram, N=0~12
760
Figure 6.16-6 Sample Module Conversion Priority Arbitrator Diagram
761
Table 6.16.5-1 the Relation between Resolution and Conversion Cycles
762
Figure 6.16-7 Specific Sample Module ADC EOC Signal for ADINT0~3 Interrupt
763
Figure 6.16-8 PWM-Triggered ADC Start Conversion
764
Figure 6.16-9 External Triggered ADC Start Conversion
764
Figure 6.16-10 Conversion Start Delay Timing Diagram
765
Figure 6.16-11 EADC0_ST De-Bounce Timing Diagram
766
Figure 6.16-12 ADC Extend Sampling Timing Diagram
767
Figure 6.16-13 ADC Conversion Result Monitor Logics Diagram
767
Figure 6.16-14 ADC Controller Interrupts
768
Figure 6.16-15 ADC Start up Sequence with Calibration
769
Table 6.16.5-2 EADC Power Saving Mode
769
Figure 6.16-16 Model of the Sampling Network
770
Table 6.16.5-3 EADC Minimum Sampling Time
770
Register Map
771
Register Description
774
I 2 S Controller (I 2 S)
801
Overview
801
Features
801
Block Diagram
802
Basic Configuration
802
Figure 6.17-1 I 2 S Controller Block Diagram
802
Functional Description
803
Figure 6.17-2 I 2 S Clock Control Diagram
803
Figure 6.17-3 Master Mode Interface Block Diagram
803
Figure 6.17-4 Slave Mode Interface Block Diagram
804
Figure 6.17-5 I 2 S Channel Width and Data Width (CHWIDTH≦DATWIDTH)
804
Figure 6.17-6 I 2 S Channel Width and Data Width (CHWIDTH > DATWIDTH)
804
Figure 6.17-7 I 2 S Data Format Timing Diagram (FORMAT = 0X0 ; CHWIDTH≦DATWIDTH)
805
Figure 6.17-8 MSB Justified Data Format (FORMAT = 0X1 ; CHWIDTH > DATWIDTH)
805
Figure 6.17-9 LSB Justified Data Format (FORMAT = 0X2 ; CHWIDTH > DATWIDTH)
805
Figure 6.17-10 Standard PCM Audio Timing Diagram (FORMAT = 0X4 ; CHWIDTH≦DATWIDTH)
806
Figure 6.17-11 PCM with MSB Justified Data Format (FORMAT = 0X5 ; CHWIDTH > DATWIDTH)
806
Figure 6.17-12 PCM with LSB Justified Data Format (FORMAT = 0X6 ; CHWIDTH > DATWIDTH)
806
Figure 6.17-13 TDM 6-Channel Audio Format with 24-Bit Data in 32-Bit Channel Block (PCM Standard Data Format; Format=0X4)
807
Figure 6.17-14 TDM 6-Channel Audio Format with 24-Bit Data in 32-Bit Channel Block (PCM with MSB Justified; Format=0X5)
807
Figure 6.17-15 TDM 6-Channel Audio Format with 24-Bit Data in 32-Bit Channel Block (PCM with LSB Justified; Format=0X6)
807
Figure 6.17-16 I 2 S Interrupts
809
Figure 6.17-17 FIFO Contents for Various 2-Channel Audio Modes
810
Figure 6.17-18 FIFO Contents for Various 4-Channel Audio Modes
811
Figure 6.17-19 FIFO Contents for Various 6-Channel Audio Modes (Part-1)
812
Figure 6.17-20 FIFO Contents for Various 6-Channel Audio Modes (Part-2)
813
Register Map
814
Register Description
815
USB 1.1 Device Controller (USBD)
833
Overview
833
Features
833
Block Diagram
834
Basic Configuration
834
Figure 6.18-1 USB Block Diagram
834
Functional Description
835
Figure 6.18-2 NEVWK Interrupt Operation Flow
836
Figure 6.18-3 Endpoint SRAM Structure
837
Figure 6.18-4 Setup Transaction Followed by Data in Transaction
837
Figure 6.18-5 Data out Transfer
838
Register Map
839
Register Description
842
Digital Microphone Inputs (DMIC)
866
Overview
866
Features
866
Block Diagram
866
Basic Configuration
866
Figure 6.19-1 DMIC Block Diagram
866
Functional Description
867
Figure 6.19-2 DMIC Clock Control Diagram
867
Table 6.19.5-1 Example for DMIC Bus Clock and OSR Configuring
868
Figure 6.19-3 Typical Connection to Two Digital Microphones Sharing a Common Data Line
869
Figure 6.19-4 Digital Microphone Interface Timing Diagram
869
Figure 6.19-5 DMIC FIFO Contents for Various Settings
870
Register Map
871
Register Description
872
Voice Active Detection (VAD)
879
Overview
879
Features
879
Block Diagram
879
Basic Configuration
879
Functional Description
879
Figure 6.20-1 VAD Block Diagram
879
Figure 6.20-2 VAD Clock Control Diagram
880
Figure 6.20-3 VAD Data Diagram
881
Figure 6.20-4 VAD Decision Tree
882
Table 6.20.5-1 Short Term Power Attack Time Selection
883
Table 6.20.5-2 Long Term Power Attack Time Selection
883
Table 6.20.5-3 Power Threshold Reference
884
Register Map
885
Register Description
886
Audio DPWM Modulator (DPWM)
897
Overview
897
Features
897
Block Diagram
897
Basic Configuration
897
Figure 6.21-1 DPWM Block Diagram
897
Functional Description
898
Figure 6.21-2 DPWM Clock Control Diagram
899
Figure 6.21-3 Splitter Frequency Response and Channel Distribution
902
Figure 6.21-4 Audio DPWM FIFO Contents for Various Data Width
903
Register Map
905
Register Description
910
7 Electrical Characteristics
922
8 Application Circuit
923
9 Package Dimensions
924
QFN 48L (6X6X0.8 MM Pitch 0.4 MM)
924
LQFP 64L (7X7X1.4 MM Footprint 2.0 MM)
925
LQFP 64L (10X10X1.4 MM Footprint 2.0 MM)
926
10 Revision History
927
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