Nuvoton ISD91500 Manuals

Manuals and User Guides for Nuvoton ISD91500. We have 1 Nuvoton ISD91500 manual available for free PDF download: Technical Reference Manual

Nuvoton ISD91500 Technical Reference Manual (500 pages)

Multi-Algorithm Voice Processor With Headphone Driver

Brand: Nuvoton | Category: Computer Hardware | Size: 4 MB

Table of Contents
2
General Description
11
Features
11
Part Information and Pin Configuration
15
LQFP 64-Pin Diagram
15
I91535Adi
15
Figure 3.1-1 I91535ADI Pin Diagram
15
I91535H02Di
16
Figure 3.1-2 LQFP64 Type2 Pin Diagram
16
QFN 48-Pin Diagram
17
I91535Aqi
17
Figure 3.2-1 QFN48 Type1 Pin Diagram
17
I91535H02Qi
18
Figure 3.2-2 QFN48 Type2 Pin Diagram
18
Pin/Pad Description
19
Lqfp64
19
Qfn48
26
Pin Alternate Function
31
Table 3.4-1 Alternate Function Table of GPIO
31
Block Diagram
33
Figure 4-1 Functional Block Diagram 1
33
Figure 4-2 Functional Block Diagram 2
33
Functional Description
34
ARM Cortex -M0 Core
34
Figure 5.1-1 Functional Block Diagram
34
System Manager
36
Overview
36
System Memory Map
36
Table 5.2-1 Address Space Assignments for On-Chip Modules
36
System Manager Control Registers
38
System Timer (SYST)
84
Nested Vectored Interrupt Controller (NVIC)
89
Table 5.2-2 Exception Model
89
Table 5.2-3 System Interrupt Map
90
Table 5.2-4 Vector Table Format
91
System Control Registers
133
Clock Controller
141
Overview
141
Figure 5.3-1 Clock Tree
142
Clock Generator
143
System Clock
143
Figure 5.3-2 Clock Generator Block Diagram
143
Peripheral Clock
144
Power Management
144
Figure 5.3-3 System Clock Block Diagram
144
Register Map
146
Register Description
147
Table 5.3-1 the Symbol Definition of PLL Output Frequency Formula
170
Sram
172
Overview
172
Block Diagram
172
Figure 5.4-1 SRAM Controller Block Diagram
172
General Purpose I/O (GPIO)
173
Overview
173
Features
173
Block Diagram
174
Functional Description
174
Figure 5.5-1 GPIO Controller Block Diagram
174
Figure 5.5-2 Push-Pull Output
175
Figure 5.5-3 Open-Drain Output
175
Register Map
176
Register Description
178
PWM Generator and Capture Timer (PWM)
186
Overview
186
Features
186
Block Diagram
187
Figure 5.6-1 PWM Generator Architecture Diagram
187
Figure 5.6-2 PWM Generator Clock Source Control
187
Functional Description
188
Figure 5.6-3 PWM Timer Operation Timing
188
Figure 5.6-4 PWM Controller Output Duty Ratio
189
Figure 5.6-5 Dead Zone Generation Operation
189
Figure 5.6-6 Capture Operation Timing
191
Register Map
192
Register Description
193
Serial Peripheral Interface (SPI)
207
Overview
207
Features
207
Block Diagram
208
Functional Description
208
Figure 5.7-1 SPI Block Diagram
208
Figure 5.7-2 SPI Master Mode Application Block Diagram
209
Figure 5.7-3 SPI Slave Mode Application Block Diagram
209
Figure 5.7-4 Word Sleep Suspend Mode
211
Figure 5.7-5 Byte Re-Ordering Transfer
211
Figure 5.7-6 Byte Order in Memory
212
Figure 5.7-7 Byte Order in Memory
213
Figure 5.7-8 Bit Sequence of Dual Output Mode
215
Figure 5.7-9 Bit Sequence of Dual Input Mode
216
Figure 5.7-10 Quad Mode System Architecture
216
Figure 5.7-11 Bit Sequence of Quad Output Mode
217
Figure 5.7-12 FIFO Mode Block Diagram
218
Figure 5.7-13 SPI Timing in Master Mode
219
Figure 5.7-14 SPI Timing in Master Mode (Alternate Phase of SPICLK)
220
Figure 5.7-15 SPI Timing in Slave Mode
220
Figure 5.7-16 SPI Timing in Slave Mode (Alternate Phase of SPICLK)
221
Register Map
224
Register Description
225
I 2 S Controller (I 2 S)
241
Overview
241
Features
241
Block Diagram
241
Figure 5.8-1 I2S Block Diagram
241
Functional Description
242
Figure 5.8-2 I 2 S Clock Control Diagram
242
Figure 5.8-3 Master Mode Interface Block Diagram
242
Figure 5.8-4 Slave Mode Interface Block Diagram
243
Figure 5.8-5 I 2 S Channel Width and Data Width (CHWIDTH≦DATWIDTH)
243
Figure 5.8-6 I 2 S Channel Width and Data Width (CHWIDTH > DATWIDTH)
243
Figure 5.8-7 I 2 S Data Format Timing Diagram (FORMAT = 0X0 ; CHWIDTH≦DATWIDTH)
244
Figure 5.8-8 MSB Justified Data Format (FORMAT = 0X1 ; CHWIDTH > DATWIDTH)
244
Figure 5.8-9 LSB Justified Data Format (FORMAT = 0X2 ; CHWIDTH > DATWIDTH)
244
Figure 5.8-10 Standard PCM Audio Timing Diagram (FORMAT = 0X4 ; CHWIDTH≦DATWIDTH)
245
Figure 5.8-11 PCM with MSB Justified Data Format (FORMAT = 0X5 ; CHWIDTH > DATWIDTH)
245
Figure 5.8-12 PCM with LSB Justified Data Format (FORMAT = 0X6 ; CHWIDTH > DATWIDTH)
245
Figure 5.8-13 I 2 S Interrupts
247
Figure 5.8-14 FIFO Contents for Various 2-Channel Audio Modes
248
Register Map
249
Register Description
250
Timer Controller (TMR)
265
Overview
265
Features
265
Block Diagram
265
Figure 5.9-1 Timer Controller Block Diagram
265
Functional Description
266
Figure 5.9-2 Clock Source of Timer Controller
266
Figure 5.9-3 Continuous Counting Mode
267
Register Map
268
Register Description
269
Watchdog Timer (WDT)
275
Overview
275
Features
275
Block Diagram
275
Functional Description
275
Figure 5.10-1 Watchdog Timer Block Diagram
275
Figure 5.10-2 WDT Clock Control Diagra
275
Table 5.10-1 Watchdog Timeout Interval Selection
276
Register Map
277
Register Description
278
I 2 C Serial Interface Controller (I 2 C)
280
Overview
280
Features
280
Functional Description
280
Figure 5.11-1 I2C Bus Timing
281
Figure 5.11-2 I2C Protocol
281
Figure 5.11-3 Master Transmits Data to Slave
282
Figure 5.11-4 Master Reads Data from Slave
282
Figure 5.11-5 START and STOP Condition
282
Figure 5.11-6 Bit Transfer on the I2C Bus
283
Figure 5.11-7 Acknowledge on the I2C Bus
283
Figure 5.11-8 Legend for the Following Four Figures
285
Figure 5.11-9 Master Transmitter Mode
286
Figure 5.11-10 Master Receiver Mode
287
Figure 5.11-11 Slave Transmitter Mode
288
Figure 5.11-12 Slave Receiver Mode
289
Figure 5.11-13 GC Mode
290
Figure 5.11-14 I2C Data Shift Direction
292
Figure 5.11-15 I2C Time-Out Count Block Diagram
293
Register Map
294
Register Description
295
12-Bit Analog-To-Digital Converter (SARADC)
303
Overview
303
Features
303
Block Diagram
303
Figure 5.12-1 ADC Controller Block Diagram
304
Functional Description
305
Figure 5.12-2 SARADC Clock Source
306
Figure 5.12-3 Continuous Scan on Selected Channels
307
Figure 5.12-4 Single-Cycle Scan on Selected Channels
308
Figure 5.12-5 A/D Conversion Result Comparison
308
Figure 5.12-6 A/D Controller Interrupt
309
Register Map
310
Register Description
311
PDMA Controller (PDMA)
325
Overview
325
Features
325
Block Diagram
325
Figure 5.13-1 PDMA Controller Block Diagram
325
Functional Description
326
Register Map
327
Register Description
328
UART Interface Controller (UART)
345
Overview
345
Features
345
Block Diagram
345
Figure 5.14-1 UART Clock Control Diagram
345
Functional Description
346
Table 5.14-1 UART Baud Rate Equation
346
Table 5.14-2 UART Baud Rate Setting Table
346
Figure 5.14-2 UART Block Diagram
346
Figure 5.14-3 Auto Flow Control Block Diagram
348
Register Map
349
Register Description
350
Table 5.14-3 UART Interrupt Sources and Flags Table in Software Mode
363
Table 5.14-4 UART Interrupt Sources and Flags Table in DMA Mode
363
Table 5.14-5 Baud Rate Equations
366
Flash Memory Controller (FMC)
367
Overview
367
Features
367
Flash Memory Controller Block Diagram
367
Flash Memory Organization
368
Table 5.15-1 Memory Address Map
368
Figure 5.15-1 Flash Memory Control Block Diagram
368
Boot Selection
369
Figure 5.15-2 Flash Memory Organization
369
Figure 5.15-3 Boot Select (BS) for Power-On Action
369
Data Flash (DATAF)
370
Table 5.15-2 Data Flash Table
370
Figure 5.15-4 Program Executing Range for Boot from APROM and Boot from LDROM
370
Figure 5.15-5 Flash Memory Structure
371
User Configuration (CONFIG)
372
In-System Programming (ISP)
376
ISP Procedure
376
Figure 5.15-6 ISP Operation Timing
376
Figure 5.15-7 Boot Sequence and ISP Procedure
377
Table 5.15-3 ISP Command Set
378
Register Map
379
Register Description
380
USB 1.1 Device Controller (USBD)
387
Overview
387
Features
387
Block Diagram
388
Basic Configuration
388
Figure 5.16-1 USB Block Diagram
388
Functional Description
389
Figure 5.16-2 NEVWK Interrupt Operation Flow
390
Figure 5.16-3 Endpoint SRAM Structure
391
Figure 5.16-4 Setup Transaction Followed by Data in Transaction
391
Figure 5.16-5 Data out Transfer
392
Register Map
393
Register Description
396
Companding (CPD)
423
Overview
423
Features
423
Functional Description
423
Figure 5.17-1 CPD Controller Interrupt
424
Register Map
425
Register Description
426
Digital-To-Analog Converter with Headphone Driver Output (DAC)
435
Overview
435
Features
435
Block Diagram
435
Functional Description
435
Figure 5.18-1 DAC Function Block Diagram
435
Figure 5.18-2 DAC Clock Control Diagram
436
Table 5.18-1 Effective OSR for Different OSR_DIV Setting
437
Table 5.18-2 Effective OSR for Special Oversampling Ratio
437
Table 5.18-3 Sample Rates for CLKSET (DAC_CTL0[31]) = 0
437
Table 5.18-4 Sample Rates for CLKSET (DAC_CTL0[31]) = 1
438
Figure 5.18-3 Audio DAC FIFO Contents for 8Bits
438
Figure 5.18-4 Audio DAC FIFO Contents for 16Bits
439
Figure 5.18-5 Audio DAC FIFO Contents for 24Bits
439
Figure 5.18-6 Audio DAC FIFO Contents for 32Bits
439
Figure 5.18-7 Audio DAC FIFO Pointer Block
440
Figure 5.18-8 Headphone Output Clamp Options
441
Table 5.18-5 DAC_ANA1 Register Setting in each Phase
443
Register Map
444
Register Description
445
Sigma- Delta Analog-To-Digital Converter (SDADC)
460
Overview
460
Features
460
Block Diagram
460
Functional Description
460
Figure 5.19-1 SDADC Function Block Diagram
460
Figure 5.19-2 SDADC Clock Control Diagram
461
Figure 5.19-3 SDADC Sample Rate Diagram
461
Table 5.19-1 Sample Rates for MCLK 24.576Mhz(BIQ on SDADC)
462
Table 5.19-2 Sample Rates for MCLK 12.288Mhz(BIQ on SDADC)
463
Table 5.19-3 Sample Rates for SDADC Source Clock from HIRC 48Mhz(BIQ on SDADC)
464
Figure 5.19-4 Audio SDADC FIFO Contents
464
Figure 5.19-5 SDADC Controller Interrupt
466
Register Map
467
Register Description
468
Analog Functional Blocks (ANA)
484
Overview
484
Features
484
Functional Description
484
Figure 5.20-1 VMIDH/L Reference Generation
484
Figure 5.20-2 MICBIAS Block Diagram
485
Figure 5.20-3 MICBIAS Application Diagram
485
Register Map
486
Register Description
487
Biquad Filter (BIQ)
490
Overview
490
Features
490
Funtion Description
490
Register Map
492
Register Description
494
Revision History
499

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Nuvoton ISD91500 Technical Reference Manual (500 pages)

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