Figure 6.9-3 Watchdog Timer Time-Out Interval And Reset Period Timing; Table 6.9.5-1 Watchdog Timer Time-Out Interval Period Selection - Nuvoton ISD94124BYI Technical Reference Manual

011
100
101
110
111

Table 6.9.5-1 Watchdog Timer Time-out Interval Period Selection

T
WDT
WDT_CLK
RSTEN
(WDT_CTL[1])
IF
(WDT_CTL[3])
RSTF
(WDT_CTL[2])
WDT reset
(low reset)
•
T : Watchdog Clock Time Period
WDT
•
T : Watchdog Time-out Interval Period ( (2
TIS
•
T : Watchdog Reset Delay Period
RSTD
- Selectable 3/18/130/1026 * T
by RSTDSEL(WDT_ALTCTL [1:0])
•
T : Watchdog Reset Period ( 63 * T
RST

Figure 6.9-3 Watchdog Timer Time-out Interval and Reset Period Timing

6.9.5.3 WDT Wake-up
If WDT clock source is selected to 10 kHz or LXT, system can be waken-up from Power-down
mode while WDT time-out interrupt signal is generated and WKEN (WDT_CTL[4]) enabled. Notice
that user should set LXTEN (CLK_PWRCTL [1]) or LIRCEN (CLK_PWRCTL [3]) to select clock
source before system entries Power-down mode because the system peripheral clock are disabled
when system is Power-down mode. In the meanwhile, the WKF (WDT_CTL[5]) will set to 1
automatically, user can check WKF (WDT_CTL[5]) status by software to recognize the system has
been waken-up by WDT time-out interrupt or not.
6.9.5.4 WDT ICE Debug
When ICE is connected to MCU, WDT counter is counting or not by ICEDEBUG (WDT_CTL[31]).
The default value of ICEDEBUG is 0, WDT counter will stop counting when CPU is held by ICE. If
ICEDEBUG is set to 1, WDT counter will keep counting no matter CPU is held by ICE or not.
Sep 9, 2019
ISD94100 Series Technical Reference Manual
10
2 * T
WDT
12
2 * T
WDT
14
2 * T
WDT
16
2 * T
WDT
18
2 * T
WDT
T
TIS
4
~ 2
delay period controlled
WDT
)
WDT
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(3/18/130/1026) * T
(3/18/130/1026) * T
(3/18/130/1026) * T
(3/18/130/1026) * T
(3/18/130/1026) * T
RSTF = 1
IF = 1 (if RSTEN = 1)
T
RSTD
T
18
) * T )
WDT
WDT
WDT
WDT
WDT
WDT
RST
Rev1.09