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3.5
Word Alignment
Since instruction and data are accessed in byte units, the addresses to be placed
depend on the instruction length and data width.
■ Program Access
Programs for the MB91260B series must be located at an address that is a multiple of the number 2.
Bit0 in the PC (program counter) is set to "0" when the PC is updated as an instruction is executed. Bit0
may be set to "1" only when an odd-numbered address is specified as the branch destination address. Even in
that case, bit0 is invalid and the instruction must be placed at an address that is a multiple of the number 2.
There is no odd-numbered address exception.
■ Data Access
When accessing data, the FR family forces alignment of the address depending on the access width as
follows:
Word access
Half word access
Byte access
When word or halfword access is performed, some of the bits in the effective address obtained by
calculation are forced to be "0". In the addressing mode with @(R13, Ri), for example, the register before
addition (e.g., even with the LSB containing "1") is used for calculation as it is and the lower bits in the
result of addition are masked. The register before calculation is not masked.
[Example] : LD@ (R13, R2) , R0
: The address is a multiple of the number 4 (with the two LSBs forced to be "00
: The address is a multiple of the number 2 (with the LSB forced to be "0").
: –
R13
0 0 0 0 2 2 2 2
R2
0 0 0 0 0 0 0 3
+)
Result of addition
Address pin
CHAPTER 3 CPU AND CONTROL UNITS
H
H
0 0 0 0 2 2 2 5
H
↓ Lower two bits are forced to be masked.
0 0 0 0 2 2 2 4
H
").
B
41
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