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20.1.2 Standby function control register
The wait time after the STOP mode is released upon interrupt request is controlled with the oscillation stabilization
time select register (OSTS).
OSTS is set by an 8-bit memory manipulation instruction.
RESET input sets the value of this register to 04H.
Figure 20-1. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFAH After reset: 04H R/W
Symbol
7
OSTS
0
OSTS2
0
0
0
0
1
Other than above
Caution The wait time after the STOP mode is released does not include the time (see "a" in the illustration
below) from STOP mode release to clock oscillation start. The time is not included either by
RESET input or by interrupt request generation.
Remarks 1. f
: Main system clock oscillation frequency
X
2. Values in parentheses are for operation with f
CHAPTER 20 STANDBY FUNCTION
6
5
4
0
0
0
OSTS1
OSTS0
12
0
0
2
/f
X
14
0
1
2
/f
X
15
1
0
2
/f
X
16
1
1
2
/f
X
17
0
0
2
/f
X
Setting prohibited
STOP mode release
X1 pin voltage
waveform
User's Manual U15798EJ2V0UD
3
2
0
OSTS2
Oscillation stabilization time selection
(410 µ s)
(1.64 ms)
(3.28 ms)
(6.55 ms)
(13.1 ms)
a
= 10 MHz.
X
1
0
OSTS1
OSTS0
407
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