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10.3 Watchdog Timer Control Register
The following two types of registers are used to control the watchdog timer.
• Timer clock select register 2 (TCL2)
• Watchdog timer mode register (WDTM)
(1) Timer clock select register 2 (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Symbol
7
6
5
TCL2
0
0
0
TCL22
TCL21
TCL20
0
0
0
0
1
0
1
0
0
1
1
0
Other than above
Remark
f
:
System clock oscillation frequency (ceramic/crystal oscillation)
X
f
: System clock oscillation frequency (RC oscillation)
CC
CHAPTER 10 WATCHDOG TIMER
Figure 10-2. Timer Clock Select Register 2 Format
4
3
2
1
0
0
TCL22 TCL21 TCL20
Watchdog timer count clock selection
At f
= 5.0-MHz operation At f
= 4.0-MHz operation
X
CC
4
f
/2
(312.5 kHz)
f
/2
X
CC
6
f
/2
(78.1 kHz)
f
/2
CC
X
8
f
/2
f
/2
(19.5 kHz)
CC
X
10
f
/2
(4.88 kHz)
f
/2
X
CC
Setting prohibited
User's Manual U13045EJ2V0UM00
0
Address
After reset
FF42H
00H
At f
= 5.0-MHz operation
X
µ
11
4
2
/f
(410 s)
(250 KHZ)
X
6
13
(62.5 KHZ)
2
/f
(1.64 ms)
X
8
15
(15.6 KHZ)
2
/f
(6.55 ms)
X
17
10
(3.91 KHZ)
2
/f
(26.2 ms)
X
R/W
R/W
Interval time
At f
= 4.0-MHz operation
CC
µ
11
2
/f
(512 s)
CC
13
2
/f
(2.05 ms)
CC
15
2
/f
(8.19 ms)
CC
17
2
/f
(32.8 ms)
CC
131
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