NEC V850E/PH2 User Manual page 1051

Edition No.
EE3 Figure 16-4 "CSIBn Control Register 0 (CBnCTL0) (1/2)", changed
Figure 17-2" Clocked Serial Interface Mode Register 3n (CSIM3n) (1/2)",
Note added
Figure 17-3 "Clocked Serial Interface Clock Select Register 3n (CSIC3n)
(1/3)", Note added
Figure 17-4 "Receive Data Buffer Register 3n (SIRB3n, SIRB3nL,
SIRB3nH)", Note added
Figure 17-5 "Chip Select CSI Buffer Register 3n (SFCS3n, SFCS3nL)",
Note added
Figure 17-6 "Transmit Data CSI Buffer Register 3n (SFDB3n, SFDB3nL,
SFDB3nH)", Note added
Figure 17-7 "CSIBUF Status Register 3n (SFA3n)(1/3)", Note added
Figure 17-8 "Transfer Data Length Select Register 3n (CSIL3n)", Note
added
Figure 17-9 "Transfer Data Number Specification Register 3n (SFN3n)",
Note added
18 "AFCAN Controller", introduction changed
Figure 24-2 "Flash Memory Mapping of µPD70F3447", values changed
Appendix B Revision History
Major items revised
User's Manual U16580EE3V1UD00
(5/5)
Revised Sections
16.3 (1), p. 647
17.3 (1), p. 678
17.3 (2), p. 680
17.3 (3), p. 683
17.3 (4), p. 684
17.3 (5), p. 685
17.3 (6), p. 686
17.3 (7), p. 689
17.3 (8), p. 690
18, p. 737
24.2, p. 965
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