NEC V850E/PH2 User Manual page 1049

Edition No.
EE2 Figure 11-6 "TMTn Control Register 0 (TTnCTL0)", changed
Figure 11-7 "TMTn Control Register 1 (TTnCTL1)", changed
Figure 11-8 "TMTn Control Register 2 (TTnCTL2)", changed
Figure 11-9 "TMTn I/O Control Register 0 (TTnIOC0)", changed
Figure 11-11 "TMTn I/O Control Register 2 (TTnIOC2)", changed
Figure 11-12 "TMTn I/O Control Register 3 (TTnIOC3)", changed
Figure 11-13 "TMTn Option Register 0 (TTnOPT0)", changed
Figure 11-14 "TMTn Option Register 1 (TTnOPT1)" changed
Table 11-6 "Counter Clear Operation" changed
Table 11-7 "Capture/Compare Rewrite Methods in Each Mode" changed
11.6.9 "Encoder count function" changed
11.6.9 (6) (a) removed
Figure 11-37 (a) removed, ((c) changed, (i) and (j) removed
Figure 11-38 "Basic Timing in Offset Trigger Generation Mode" changed
Figure 14-1 "Block Diagram of A/D Converter (ADCn)", changed
Figure 14-5 "A/D Converter n Trigger Source Select Register (ADTRSELn)",
changed
14.4.2 (1) (b) "Timer trigger mode", bit names changed
14.6 "Operation in Timer Trigger Mode",
timer event signals's names changed
14.6.1 (1) "1-buffer mode operation (timer trigger select: 1 buffer)",
timer event signals's names changed
Table 14-6 "Correspondence Between Analog Input Pins and ADCRnm
Register (1-Buffer Mode (Timer Trigger Select: 1 Buffer)", changed
Figure 14-15 "Example of 1-Buffer Mode Operation (Timer Trigger Select: 1
Buffer) (ANIn1)", changed
14.6.1 (2) "4-buffer mode operation (timer trigger select: 4 buffers)",
timer event signals's names changed
Table 14-7 "Correspondence Between Analog Input Pins and ADCRnm
Register (4-Buffer Mode (Timer Trigger Select: 4 Buffers)", changed
Figure 14-16 "Example of 4-Buffer Mode Operation (Timer Trigger Select:
4 Buffers) (ANIn3)", changed
Table 14-8 "Correspondence Between Analog Input Pins and ADCRnm
Register (Scan Mode (Timer Trigger Scan))", changed
Figure 14-17 "Example of Scan Mode Operation (Timer Trigger Scan)
(ANIn0 to ANIn4)", changed
Figure 15-4 "UARTCn Control Register 2 (UCnCTL2)", changed
Figure 16-28 "Prescaler Compare Registers 0 and 1 (PRSCM0, PRSCM1)",
changed
Figure 17-20 "Delay Control of Transmission/Reception Completion
Interrupt (INTC3n)", changed
Figure 17-21 "Transfer Wait Function" (3/3),
CSITn bit value changed from 0 to 1
Figure 18-24 "CAN Global Clock Selection Register (CnGMCS)",
Bit 7 changed, Remark 1 changed
Table 20-1 "Port Type and Function Overview", Port CD changed
Appendix B Revision History
Major items revised
User's Manual U16580EE3V1UD00
(3/5)
Revised Sections
11.4 (1), p.452
11.4 (2), p.453
11.4 (3), p.455-456
11.4 (4), p.457
11.4 (6), p.459
11.4 (7), p.460, 461
11.4 (8), p.462
11.4 (9), p.464
11.5.1 (2), p.467
11.5.2 82), p.472
11.6.9, p.499-500
11.6.9 (6), p.512
11.6.9 (6), p. 512-518
11.6.10, p.517
14.2, p.559
14.3 (4), p.564
14.4.2 (1) (b), p.570
14.6, p.580
14.6.1 (1), p.580
14.6.1, p.581
14.6.1, p.581
14.6.1 (2), p.582
14.6.1, p.582
14.6.1, p.583
14.6.2, p.584
14.6.2, p.585
15.3 (3), p.599
16.7.2 (2), p.659
17.5.14, p.692
17.5.15, p.695
18.6.2, p.761
20.2.1, p.865
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