Format Of Serial Clock Selection Register 10 (Csic10) - NEC 78K0 User Manual

(2) Serial clock selection register 1n (CSIC1n)
This register specifies the timing of the data transmission/reception and sets the serial clock.
CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
µ
Remark n = 0: PD780143, 780144
µ
n = 0, 1: PD780146, 780148, 78F0148
Figure 16-5. Format of Serial Clock Selection Register 10 (CSIC10)
Address: FF81H After reset: 00H R/W
Symbol 7
CSIC10 0
CKP10
0
0
1
1
CKS102
0
0
0
0
1
1
1
1
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
6 5
0 0 CKP10
DAP10 Specification of data transmission/reception timing
0
SCK10
SO10
SI10 input timing
1
SCK10
SO10
SI10 input timing
0
*
SCK10
SO10
SI10 input timing
1
SCK10
SO10
SI10 input timing
CKS101 CKS100
0 0 f /2 (5 MHz)
X
0 1 f /2
X
1 0 f /2
X
1 1 f /2
X
0 0 f /2
X
0 1 f /2
X
1 0 f /2
X
1 1 External clock input to SCK10
User's Manual U15947EJ2V0UD
4 3
DAP10 CKS102
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSI10 serial clock selection
2
(2.5 MHz)
3
(1.25 MHz)
4
(625 kHz)
5
(312.5 kHz)
6
(156.25 kHz)
7
(78.13 kHz)
2 1 0
CKS101 CKS100
Type
1
2
3
4
Mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
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