Figure 12-8: Asynchronous Serial Interface Transmission Completion Interrupt Timing - NEC V850E/CA1 ATOMIC Preliminary User's Manual

(2) Transmit operation
When CAE bit is set to 1 in the ASIMn register, a high level is output from the TXDn pin.
Then, when TXE bit is set to 1 in the ASIMn register, transmission is enabled, and the transmit
operation is started by writing transmit data to transmission buffer register (TXBn) (n = 0 to 2).
(a) Transmission enabled state
This state is set by the TXE bit in the ASIMn register.
• TXE = 1: Transmission enabled state
• TXE = 0: Transmission disabled state
Since UARTn does not have a CTS (transmission enabled signal) input pin, a port should be used
to confirm whether the destination is in a reception enabled state.
(b) Starting a transmit operation
In transmission enabled state, a transmit operation is started by writing transmit data to transmis-
sion buffer register (TXBn). When a transmit operation is started, the data in TXBn is transferred to
transmission shift register. Then, the transmission shift register outputs data to the TXDn pin (the
transmit data is transferred sequential starting with the start bit). The start bit, parity bit, and stop
bits are added automatically.
(c) Transmission interrupt request
When the transmission shift register becomes empty, a transmission completion interrupt request
(INTSTn) is generated. The timing for generating the INTSTn interrupt differs according to the spec-
ification of the number of stop bits. The INTSTn interrupt is generated at the same time that the last
stop bit is output.
If the data to be transmitted next has not been written to the TXBn register, the transmit operation is
suspended.
Caution: Normally, when the transmission shift register becomes empty, a transmission com-
pletion interrupt (INTSTn) is generated. However, no transmission completion inter-
rupt (INTSTn) is generated if the transmission shift register becomes empty due to
the input of a RESET.

Figure 12-8: Asynchronous Serial Interface Transmission Completion Interrupt Timing

TXDn (output)
INTSTn (output)
TXDn (output)
INTSTn (output)
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Chapter 12 Serial Interface Function
(a) Stop bit length: 1
Start
D0 D1 D2
(b) Stop bit length: 2
Start D0 D1 D2
Preliminary User's Manual U14913EE1V0UM00
D6 D7 Parity
Stop
Parity
D6 D7
Stop