Read Timing - Renesas M16C/6NK Hardware Manual

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This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
Memory Expansion Mode and Microprocessor Mode
(For setting with no wait)

Read timing

BCLK
CSi
t
d(BCLK-AD)
ADi
BHE
t
d(BCLK-ALE)
ALE
RD
DBi
Write timing
BCLK
CSi
ADi
BHE
t
ALE
WR,WRL,
WRH
DBi
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : V
Output timing voltage : V
Figure 22.6 Timing Diagram (3)
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
tcyc
t
h(BCLK-AD)
25ns.max
4ns.min
t
h(BCLK-ALE)
-4ns.min
25ns.max
t
d(BCLK-RD)
t
h(BCLK-RD)
25ns.max
t
ac1(RD-DB)
(0.5 ✕ tcyc-45)ns.max
Hi-Z
t
SU(DB-RD)
40ns.min
t
d(BCLK-CS)
25ns.max
tcyc
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE) h(BCLK-ALE)
25ns.max -4ns.min
t
d(BCLK-WR)
25ns.max
t
d(BCLK-DB)
40ns.max
Hi-Z
(0.5 ✕ tcyc-40)ns.min
= 0.8 V, V = 2.0 V
IL IH
= 0.4 V, V = 2.4 V
OL OH
page 307 of 378
22. Electric Characteristics (Normal-ver.)
4ns.min
t
h(RD-AD)
0ns.min
0ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
t
h(BCLK-DB)
4ns.min
t
t
d(DB-WR)
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
VCC = 5V