Renesas M16C/6NK Hardware Manual page 79

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M16C/6N Group (M16C/6NK, M16C/6NM)
Peripheral Clock Select Register
b7 b6 b5 b4 b3 b2
0 0 0
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. If this bit is set to "1", the software interrupt number and SFR location can be changed as follows.
(1) Software interrupt number of the key input interrupt in the vector table can be changed from 14 to 13.
- No.13 is changed from the CAN0/1 error interrupt to the CAN0/1 error/key input interrupt.
- No.14 is changed from the A/D/key input interrupt to the A/D interrupt.
(2) Address of the KUPIC register in the SFR can be changed from 004Eh to 004Dh.
- Address 004Dh is changed from the C01ERRIC register to the C01ERRIC/KUPIC register.
- Address 004Eh is changed from the ADIC/KUPIC register to the ADIC register.
3. When this bit = 1, the A/D clock is set to divide-by-1 of fAD mode regardless of whether the PCLK0 bit is set.
4. When the PCLK5 bit and the SM43 bit in the S4C register = 1, the pin function of SI/O4 can be changed as follows.
P8_0/TA4OUT/U/(SIN4)
P7_5/TA2IN/W/(SOUT4)
P7_4/TA2OUT/W/(CLK4)
5. SI/O5 and SI/O6 are only in the 128-pin version.
Figure 8.5 PCLKR Register
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
(1)
b1 b0
Symbol
PCLKR
Bit Symbol
Timers A, B, and A/D Clock
Select Bit
PCLK0
(Clock source for the timers A, B,
the dead time timer and A/D)
SI/O Clock Select Bit
(Clock source for UART0 to UART2,
PCLK1
SI/O3 to SI/O6)
-
Reserved Bit
(b4-b2)
PCLK5 Pin Function Swirch Bit
Software Interrupt Number/SFR
PCLK6
Location Switch Bit
PCLK7 A/D Clock Direct Input Bit
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Address After Reset
025Eh 00h
Bit Name
0 : Divide-by-2 of fAD, f2
1 : fAD, f1
0 : f2SIO
1 : f1SIO
(5)
Set to "0"
0: Normal mode
1: Swiching mode
0: Normal mode
1: Swiching mode
0: Normal mode
1: Swiching mode
8. Clock Generating Circuit
Function
RW
RW
RW
RW
RW
(4)
RW
(2)
RW
(3)