Renesas M16C/6NK Hardware Manual page 172

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M16C/6N Group (M16C/6NK, M16C/6NM)
UARTi Transmit/Receive Mode Register (i = 0 to 2)
b7 b6 b5 b4
NOTES:
1. To receive data, set the corresponding port direction bit for each RXDi pin to "0" (input mode).
2. Set the corresponding port direction bit for SCL and SDA pins to "0" (input mode).
3. Set the corresponding port direction bit for each CLKi pin to "0" (input mode).
UARTi Transmit/Receive Control Register 0 (i = 0 to 2)
b7 b6 b5 b4
NOTES:
1. CTS1/RTS1 can be used when the CLKMD1 bit in the UCON register = 0 (only CLK1 output) and the
RCSP bit in the UCON register = 0 (CTS0/RTS0 not separated).
2. Set the corresponding port direction bit for each CTSi pin to "0" (input mode)
3. SCL2(P7_1) is N channel open-drain output. The NCH bit in the U2C0 register is N channel open-drain
output regardless of the NCH bit.
4. The UFORM bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "001b" (clock
synchronous serial I/O mode), or "101b" (UART mode, 8-bit transfer data).
Set this bit to "1" when the SMD2 to SMD0 bits are set to "010b" (I
to SMD0 bits are set to "100b" (UART mode, 7-bit transfer data) or "110b" (UART mode, 9-bit transfer data).
5. When changing the CLK1 to CLK0 bits, set the UiBRG register.
Figure 15.6 U0MR to U2MR Registers and U0C0 to U2C0 Registers
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
b3 b2 b1 b0
Symbol
U0MR to U2MR
Bit
Symbol
SMD0
Serial Interface Mode
SMD1
Select Bit
SMD2
Internal/External Clock
CKDIR
Select Bit
Stop Bit Length
STPS
Select Bit
Odd/Even Parity
PRY
Select Bit
Parity Enable Bit
PRYE
TXD, RXD I/O Polarity
IOPOL
Reverse Bit
b3 b2 b1 b0
Symbol
U0C0 to U2C0
Bit
Symbol
CLK0
BRG Count Source
Select Bit
CLK1
CTS/RTS Function
CRS
Select Bit
Transmit Register
TXEPT
Empty Flag
CTS/RTS Disable Bit
CRD
Data Output
NCH
Select Bit
CLK Polarity
CKPOL
Select Bit
Transfer Format
UFORM
Select Bit
page 154 of 378
Address
03A0h, 03A8h, 01F8h
Bit Name
b2 b1 b0
: Serial interface disabled
0 0 0
: Clock synchronous serial I/O mode
0 0 1
2
:
0 1 0 I C mode
(1)
: UART mode transfer data 7-bit long
1 0 0
: UART mode transfer data 8-bit long
1 0 1
: UART mode transfer data 9-bit long
1 1 0
Do not set a value except above
0 : Internal clock
1 : External clock
0 : 1 stop bit
1 : 2 stop bits
Effective when the PRYE bit = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Address
03A4h, 03ACh, 01FCh
Bit Name
b1 b0
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
(5)
1 0 : f32SIO is selected
1 1 : Do not set a value
Effective when CRD = 0
0 : CTS function is selected
(1)
1 : RTS function is selected
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6_0, P6_4, P7_3 can be used as I/O ports)
0 : TXDi/SDAi and SCLi pins are CMOS output
1 : TXDi/SDAi and SCLi pins are
(3)
N channel open-drain output
0 : Transmit data is output at falling edge
of transfer clock and receive data is
input at rising edge
1 : Transmit data is output at rising edge
of transfer clock and receive data is
input at falling edge
0 : LSB first
(4) 1 : MSB first
2
C mode), and to "0" when the SMD2
15. Serial Interface
After Reset
00h
Function RW
RW
(2)
RW
RW
RW
(3)
RW
RW
RW
RW
After Reset
00001000b
Function RW
RW
RW
(2)
RW
RO
RW
RW
RW
RW