Renesas M16C/6NK Hardware Manual page 139

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M16C/6N Group (M16C/6NK, M16C/6NM)
Timer Ai Mode Register (i = 0 to 4)
(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2
0
NOTES:
1.During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
2.Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are "00b" (TAiIN pin input).
3.Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port direction
bit for TAiOUT pin is set to "0" (input mode).
Figure 13.8 TA0MR to TA4MR Registers in Event Counter Mode (when not using two-phase pulse
signal processing)
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
b1 b0
Symbol
0 1
TA0MR to TA4MR
Bit Symbol
TMOD0
Operation Mode Select Bit
TMOD1
Pulse Output Function
MR0
Select Bit
MR1
Count Polarity Select Bit
Up/Down Switching
MR2
Cause Select Bit
MR3
Set to "0" in event counter mode
Count Operation Type
TCK0
Select Bit
Can be "0" or "1" when not using two-phase pulse signal processing.
TCK1
page 121 of 378
Address After Reset
0396h to 039Ah
Bit Name
b1 b0
0 1 : Event counter mode
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output
(TAiOUT pin functions as pulse output pin)
0 : Counts falling edge of external signal
(2)
1 : Counts rising edge of external signal
0 : UDF register
1 : Input signal to TAiOUT pin
0 : Reload type
1 : Free-run type
13. Timers
00h
Function
RW
RW
(1)
RW
RW
RW
RW
(3)
RW
RW
RW