Renesas M16C/6NK Hardware Manual page 223

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M16C/6N Group (M16C/6NK, M16C/6NM)
A/D Control Register 2
b7 b6 b5 b4 b3 b2
0
NOTES:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. The φAD frequency must be 10 MHz or less. The selected φAD frequency is determined by a combination of the
CKS0 bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register.
CKS2 CKS1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
A/D Register i (i = 0 to 7)
(b15)
b7
Figure 16.3 ADCON2 Register, and AD0 to AD7 Registers
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
(1)
b1 b0
Symbol
ADCON2
Bit Symbol
A/D Conversion Method
SMP
Select Bit
ADGSEL0
A/D Input Group Select Bit
ADGSEL1
-
Reserved Bit
(b3)
Frequency Select Bit 2
CKS2
- Nothing is assigned. When write, set to "0".
(b7-b5)
When read, their contents are "0".
φAD
CKS0
0 Divide-by-4 of fAD
1 Divide-by-2 of fAD
0
fAD
1
0 Divide-by-12 of fAD
1
Divide-by-6 of fAD
0
Divide-by-3 of fAD
1
(b8)
b0 b7
When BITS bit in ADCON1
register is "1" (10-bit mode)
Low-order 8 bits of
A/D conversion result
High-order 2 bits of
A/D conversion result
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
page 205 of 378
Address After Reset
03D4h 00h
Bit Name
0 : Without sample and hold
1 : With sample and hold
b2 b1
0 0 : Port P10 group is selected
0 1 : Do not set a value
1 0 : Port P0 group is selected
1 1 : Port P2 group is selected
Set to "0"
0 : Selects fAD, divide-by-2 of fAD, or
divide-by-4 of fAD.
(2)
1 : Selects divide-by-3 of fAD, divide-by-6
of fAD, or divide-by-12 of fAD.
Symbol
AD0 03C1h to 03C0h
AD1 03C3h to 03C2h
AD2 03C5h to 03C4h
AD3 03C7h to 03C6h
AD4 03C9h to 03C8h
AD5 03CBh to 03CAh
b0
AD6 03CDh to 03CCh
AD7 03CFh to 03CEh
Function
A/D conversion result
When read, the content is
indeterminate.
16. A/D Converter
Function
Address After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
When BITS bit is "0"
(8-bit mode)
RW
RW
RW
RW
RW
RW
-
RW
RO
RO
-